From patchwork Fri Apr 16 18:59:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 422567 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp652583jaf; Fri, 16 Apr 2021 12:09:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzr87Hf2Z6CD7zYUJl97oQx+/bDNzBUvZskHRHJbc9z0g9ZLiRXif2/En93IVkuFiZTmP4u X-Received: by 2002:aca:39d6:: with SMTP id g205mr7622126oia.81.1618600192052; Fri, 16 Apr 2021 12:09:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618600192; cv=none; d=google.com; s=arc-20160816; b=P1J2D9QaByVGwqMlxHa9RifK5gQK2omgtkyfzStIh2MqNytUpbZqBq+Mf9Eqkrc84I jnsl9FmhLMKQZeKMDp/cMmntqEz7wguQuJe/IJFcJwTXCfP97grcxwn1Hn4r+nV4zvgQ DvnYBAuYRtYMWmcRr744eAFUxRwEhQldPNswTDK6rg0HYY+xomEflYHzdXLroE9RtPGM Wn8TMam+Vfjvvjb8EoASPmTsU7z6bjqAl7dx5KDgYJWSAjTEdbGYMwPsIqxDy+zd3xtH wzVzw6Ff6NYwCVsesc88vafBJeotAjlbhyXsat+S44kjRGyiv48X972l5QTISwf3iBsl 2IBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=ltiJTDnQ2/O4PJroSqmsKtH9x3MRBSXk1lOhpSYdwigP08Dkws/hNYY8gfl+rmYTcF Mt6N5b1ODXROJfyLNQ9RR8bBU9Y/fUTAMeSVGFzX57smc0aO750z9ruSpFh0UjZ6kTqZ KL0laoL3y6fWJ4o6JJaBh+iYpez6Ol4cr6hmZ7soo8Hm0c8nHkfnnnPEvWd8aUvKqYvB TJTAnYoA0nShSlvK+f3/QiAsrOczQIEz4NbfTdESKstXPUUtK3kPBclX+hhEjkgilRpk MPwvy9kwmaj1q5qhaFamG8bzX2QbeofzTH9/QylO5nxIOTh/Lr4w0yw0MCqpctVhWA5r S36w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MMXATsoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u11si1552943oth.140.2021.04.16.12.09.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Apr 2021 12:09:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MMXATsoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lXTqh-0004zh-4f for patch@linaro.org; Fri, 16 Apr 2021 15:09:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lXThj-0003jH-88 for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:35 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lXThQ-0004Kd-BK for qemu-devel@nongnu.org; Fri, 16 Apr 2021 15:00:34 -0400 Received: by mail-pg1-x532.google.com with SMTP id f29so19813372pgm.8 for ; Fri, 16 Apr 2021 12:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=MMXATsoTqhVtFU/Z+UvY//C4A0uGt6ec7aguA5lEu7IbdJt6zRnP2KqrYQQYdaQHN2 +AUks5fcaGEyoLgKW97iRMRkskzLzrmuJmYy0uwRMPtgaF/jvu5bAt9iJokz7P936Eel Wt8MngAmP6zsg1Pm5q4NUJ9igeO8aVcE2cFWcn/8gkce8HslWsgKjy+IQJtaAwEjg7D0 GIMHoV5eoG4x6rWYWKnTRWSWNYek5/hVmyU13eeNW9eQBMX9mUh62LZGc205N2Y1u64/ hBN4X8993EzPQuggOiE3ihsCiPW9zd7i9+AUwKQ0hYFfPKsO5QnadQF/L3L4ujTOGR9O IhMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4JYXrsziQJ+2kkGBxoTfc1nhhgeCmFg+itswQ++dMS0=; b=rHbxGKyAz8YGCgrEE25RnR3xx+6dmwzRBQmL4+3o94ahlITvChjZ1NdGj2Pug4Uycd l88qaNgm6GnwA53Wy0Lt1hB0VulE+eRQ12phRxF7sUO5tp+vf1cpFDGI6S3KNpBh8bDG 4Z8OhWTk1qQR8kUmYpH17Rgnx4CYrLnZhRjTAWkE+dLYVwpqhQa4nsjbthydJxRSqrt9 2OZUpPl+dS0vW0tSuOZHgZUZhZ0HuVQVSV7l6JSplMlbbHRSTZLKKhAWkk3gzN1C1JJ+ jfEwJ+/3UU/9s3x/vN3mIk2zACxQCm5nNu/bFw15eEmZr2LoE+3pxOhGRYAkx3DL1v/+ cETQ== X-Gm-Message-State: AOAM53341q8lmUPZusn06d70oATlJ6Hd7hbW1tariXJygVC7s5TpFrGq kzwGBbZPOPRGx1ryBrbvKiOChKtLuj7ixg== X-Received: by 2002:a65:6095:: with SMTP id t21mr456207pgu.383.1618599613146; Fri, 16 Apr 2021 12:00:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.12.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Date: Fri, 16 Apr 2021 11:59:42 -0700 Message-Id: <20210416185959.1520974-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210416185959.1520974-1-richard.henderson@linaro.org> References: <20210416185959.1520974-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Adjust the interface to match what has been done to the TCGv_i32 load/store functions. This is less obvious, because at present the only user of these functions, trans_VLDST_multiple, also wants to manipulate the endianness to speed up loading multiple bytes. Thus we retain an "internal" interface which is identical to the current gen_aa32_{ld,st}_i64 interface. The "new" interface will gain users as we remove the legacy interfaces, gen_aa32_ld64 and gen_aa32_st64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 +++++++++++++++++++-------------- target/arm/translate-neon.c.inc | 6 ++- 2 files changed, 49 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 52b9ca502e..7472e98f09 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, tcg_temp_free(addr); } +static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + tcg_gen_qemu_ld_i64(val, addr, index, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); +} + +static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) +{ + TCGv addr = gen_aa32_addr(s, a32, opc); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_rotri_i64(tmp, val, 32); + tcg_gen_qemu_st_i64(tmp, addr, index, opc); + tcg_temp_free_i64(tmp); + } else { + tcg_gen_qemu_st_i64(val, addr, index, opc); + } + tcg_temp_free(addr); +} + static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { @@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } +static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + +static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) +{ + gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); +} + #define DO_GEN_LD(SUFF, OPC) \ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ @@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - tcg_gen_qemu_ld_i64(val, addr, index, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - tcg_gen_rotri_i64(val, val, 32); - } - - tcg_temp_free(addr); -} - static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data); -} - -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) -{ - TCGv addr = gen_aa32_addr(s, a32, opc); - - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_rotri_i64(tmp, val, 32); - tcg_gen_qemu_st_i64(tmp, addr, index, opc); - tcg_temp_free_i64(tmp); - } else { - tcg_gen_qemu_st_i64(val, addr, index, opc); - } - tcg_temp_free(addr); + gen_aa32_ld_i64(s, val, a32, index, MO_Q); } static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index) { - gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); + gen_aa32_st_i64(s, val, a32, index, MO_Q); } DO_GEN_LD(8u, MO_UB) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index c82aa1412e..18d9042130 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, + endian | size); } tcg_gen_add_i32(addr, addr, tmp); }