From patchwork Mon Apr 19 20:22:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 424057 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp3062281jaf; Mon, 19 Apr 2021 14:12:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz808VI0BBitSkKMEl07fKf8sLvKGKQvQ4SjPL6/GOOtse47582SFcw9s0o0qbyXG4GeNah X-Received: by 2002:a92:ddc6:: with SMTP id d6mr18918968ilr.33.1618866756233; Mon, 19 Apr 2021 14:12:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618866756; cv=none; d=google.com; s=arc-20160816; b=DWQ51k7dXSWWzE4TrMQ+0VCm+UOf4O5V1BBcxZqN35qgcr6DIVdPOHAu/ahQEZDG8p jqSwjqkleYj0rIa/PDxUQGP4cgD32Z217uPfRwhiN+mZHSABF6ptAQhbwhNvWN3YdJ8y bYw0MGRyqS8hqbiBp9h7KNzbknpVQU5iusmKmZZOUbs+tudrudXoIOwN38qoS+/LRZnU 9ml9Odo8yfksrRD55lCvFE+qzyIB7lY1Usj1qJAgt3JZlNCDxbIsZ2IulwBTFO4xBIIn LbUbZFnbUxfxHb9V0WQZwmJWVwolxJ3X9QZEO/Poj6YifwIoGWngjk2eyKoOttF0CuY6 oxog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d4KAjGOIOOmhRwAXEkZoKVidF8e2kIGAWXOFwPXfIFY=; b=DiM6ZIfKPScVaM9D8qUyf5YuXQDS9tnVbJcn4ZPzSrClvDWMXEwPOephp3er+Il88t OZG+kqoKRn/4oP2IdRjasM9x+RZgvIJ83zT+7j5aZFgIEakuA5tRUVYli1rPbktpNqPO uJ5d95nTttVRG8XtwFnBVL8+cGnn3tRpdzEar9ekzSvCuGXfXASl3azJ90pL1GYqP/l8 xjujIZDAjdZFn3sxfkaXgcBSWVqI5csP2ngX7l+E/4Z8UgclXUa+NCdwn5dl/RE9Rf8E 6K59Rsne639lZ+J8Qt0FH8B2yFJsMysAA/2MLA64N7+taDrUhDaXjwSy3+3ER2JMTTYR Tf1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i8fkmY44; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f6si7494587ioq.58.2021.04.19.14.12.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Apr 2021 14:12:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i8fkmY44; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lYbC7-0007FE-LA for patch@linaro.org; Mon, 19 Apr 2021 17:12:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lYaQa-0007OW-Vb for qemu-devel@nongnu.org; Mon, 19 Apr 2021 16:23:28 -0400 Received: from mail-qv1-xf35.google.com ([2607:f8b0:4864:20::f35]:42919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lYaQW-0002Yo-7j for qemu-devel@nongnu.org; Mon, 19 Apr 2021 16:23:28 -0400 Received: by mail-qv1-xf35.google.com with SMTP id 30so17525624qva.9 for ; Mon, 19 Apr 2021 13:23:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d4KAjGOIOOmhRwAXEkZoKVidF8e2kIGAWXOFwPXfIFY=; b=i8fkmY44VK+xNbBUJaeXrzVfxX/ZC2H4osW6AVj+Y2h8sOjdWoAolL3iCQ12HZYiaM zgfqfminHVDxHTYPBM7uWnIkz1DIhTVmCL8cNwZisK8nnIoys9GPGpSi4LV9WR2kLxwH XT3hoW4pe8K3tJCDxhUx2C2D4wtljc/63Wp3M+uC6nGDAOjYCOg4cVyLlzbTNynNA5+0 wVkuXmKzecxEM0Huz6IxZgHiYGB6w2RvHDdLnDQEGpLhtk39McHzS0fYIH06wsuWL+L2 TBf+qzCyrV+brXkuz4lTs8VJSCgkx4fT/d70i3sStZYP52fRsfXUcQ4euUO6YWroHKAN M4fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d4KAjGOIOOmhRwAXEkZoKVidF8e2kIGAWXOFwPXfIFY=; b=qgquG39QrhvOxucPQkqH8t2BvnAKFRS/Ao7YGu7qRKDhP8VfwvqlfadAevZzp7aUJ4 Bhwc+1Bfua+0GOYwIBqmFe7Nn1zfyd0vSD/PdeSlhGcyae18B6AXsZU+zqtlQV/b8BHA n1LFJPi7kv0apzIb+5VCL+eSkhi+0Bf4fLGCeFIjP80DOXssO8VON5fG/2HIFbXRieDO hfatw+hpalENkEIh6SvYa8v9YzciTseGae+odkthisINdwA2fnhvwBvr/VwLxz1E9QcA V9ZlxnkGgQZvZ7pIEk4zDsu8ItHcO69jAaKRNfcIxUlYhqxLtcUoQv9CKUHoEQcgtwsj /LbQ== X-Gm-Message-State: AOAM5337H2cqFePvcnULDJXj/NocvwoXZkE9ykaMsiWhvhzdZbV5IM6D s4faDwHwEc/YdZML0sAVtmt5zPjS/p9H+IDT X-Received: by 2002:a05:6214:88d:: with SMTP id cz13mr23183596qvb.13.1618863803347; Mon, 19 Apr 2021 13:23:23 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:80c7:aba4:3594:91a:8889:c77a]) by smtp.gmail.com with ESMTPSA id c23sm10007835qtm.46.2021.04.19.13.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 13:23:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Date: Mon, 19 Apr 2021 13:22:38 -0700 Message-Id: <20210419202257.161730-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210419202257.161730-1-richard.henderson@linaro.org> References: <20210419202257.161730-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the only caller. Adjust some commentary to talk about SCTLR_B instead of the vanishing function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d46030248a..b47a58ee9a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) -{ - /* Not needed for user-mode BE32, where we use MO_BE instead. */ - if (!IS_USER_ONLY && s->sctlr_b) { - tcg_gen_rotri_i64(val, val, 32); - } -} - static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); - gen_aa32_frob64(s, val); + + /* Not needed for user-mode BE32, where we use MO_BE instead. */ + if (!IS_USER_ONLY && s->sctlr_b) { + tcg_gen_rotri_i64(val, val, 32); + } + tcg_temp_free(addr); } @@ -4987,16 +4984,13 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); TCGv_i64 t64 = tcg_temp_new_i64(); - /* For AArch32, architecturally the 32-bit word at the lowest + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. That means we don't want to do a - * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if - * for an architecturally 64-bit access, but instead do a - * 64-bit access using MO_BE if appropriate and then split - * the two halves. - * This only makes a difference for BE32 user-mode, where - * frob64() must not flip the two halves of the 64-bit data - * but this code must treat BE32 user-mode like BE32 system. + * gen_aa32_ld_i64(), which checks SCTLR_B as if for an + * architecturally 64-bit access, but instead do a 64-bit access + * using MO_BE if appropriate and then split the two halves. */ TCGv taddr = gen_aa32_addr(s, addr, opc); @@ -5056,14 +5050,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i64 n64 = tcg_temp_new_i64(); t2 = load_reg(s, rt2); - /* For AArch32, architecturally the 32-bit word at the lowest + + /* + * For AArch32, architecturally the 32-bit word at the lowest * address is always Rt and the one at addr+4 is Rt2, even if * the CPU is big-endian. Since we're going to treat this as a * single 64-bit BE store, we need to put the two halves in the * opposite order for BE to LE, so that they end up in the right - * places. - * We don't want gen_aa32_frob64() because that does the wrong - * thing for BE32 usermode. + * places. We don't want gen_aa32_st_i64, because that checks + * SCTLR_B as if for an architectural 64-bit access. */ if (s->be_data == MO_BE) { tcg_gen_concat_i32_i64(n64, t2, t1);