From patchwork Mon Jun 28 13:58:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 467992 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4017156jao; Mon, 28 Jun 2021 07:05:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfhsdb049bH6SW4xdBK46edRxGjYOtAWFFEqC8KaI8YDydUfcpsjc92cr98yEzyUCzrtfi X-Received: by 2002:a67:be05:: with SMTP id x5mr899174vsq.26.1624889133744; Mon, 28 Jun 2021 07:05:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624889133; cv=none; d=google.com; s=arc-20160816; b=hPkQLl+J6xOC1tlsLQ3apX6/wcCYXTywY37dtV2JnLP9OlZeCVJcmvGATYlZ1Sh3Jv 1YDCrJ5SVYqUH0nqV4xjvfM2JaFt9i3PxPA6k0KBrzOE2wX3wAI2qF010cAggIhDmVGw kSBWDbh9iTA7SA2M7yqC9GntdKa1Zirs4Z1jk1WILQh2x2OxaOQfvc1BBIF3JHcQZqjB K4arxLJ9Oo3Iba/p2E2axvf3QYuCSzCaeydfc9hF2v9YchGGQTl+nTAtWDEtPdwiLmwT caLXpoSOgMS52VBtPF88IUJdUK8c+lAcvLXD8yLLPNQHACzMkkifu0qwqMJkng8r/gXd tJOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MBFvaiC9HPUxDYn9mI/RWJII1rG7bgB9MV0/lYAgXVI=; b=SvXTpAoM2c+2lA8BWuj6DnPu/FMk4DYWDXHl0c/KWBAw0iksaFQWtr8MQQ5goZmjK8 f/jZF3FZGHTglc5LVVbe1Uu/lqGSzNCOjwQN1Jw3ckE4Dp1l1Wz76K681qyQmgld5zqn o1e3ZPI0sjWFWIhwAhtDkKy/0hIznSfYkV2+bkKYg8kS47dRmqH/Uu3rzRCDBB5T+301 ADhkbkGIpRBjN2WQRIqSxMMMqDpdYI4Oue1I6jTmq0w5uqfosb7a9DA3aRbsuTKHIKD/ iCU569po4TYqEWLpb21BjQUmIkeP1zCdzuzLyX5oDEHlQMzMBXHZIrjmyRyQrlS0ufYk WD3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gBRRBa9J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b21si8487378uan.22.2021.06.28.07.05.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jun 2021 07:05:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gBRRBa9J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lxrtF-0003AT-0a for patch@linaro.org; Mon, 28 Jun 2021 10:05:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lxrmt-0003E8-PO for qemu-devel@nongnu.org; Mon, 28 Jun 2021 09:59:00 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:40550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lxrme-00064Z-EX for qemu-devel@nongnu.org; Mon, 28 Jun 2021 09:58:59 -0400 Received: by mail-wm1-x336.google.com with SMTP id o33-20020a05600c5121b02901e360c98c08so12075313wms.5 for ; Mon, 28 Jun 2021 06:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MBFvaiC9HPUxDYn9mI/RWJII1rG7bgB9MV0/lYAgXVI=; b=gBRRBa9JtJQVoHuuyVXNIuzL5seIETOZQjmysYlBqZCYVZ36z8iP7Lk28CgRpnLPNm KyJj4ZqJ0jetyD4dQpSTLRRudt9Ynp9/qSeV1xc/uH6B3GgYZL/vNxKo4oWVSEPzG2IO VKYHIfRWiMQ76Z0m4p20cF+8YFQvuWwWgEpoUuQ0LlwBh1Nu1W9+Ly0bhB2wKKc3ZtXh xUJ66nk+DTivQAPQVsnYGV2JIrcgmaXPVJHmmkqfc2IzR4RK3/CEjO+TE8ABWn/SWoUn qgqHwZlMkJyoLVFJKgR3B4LXL8OQrw5pymg1MwDGqCDsaK28660xYQZjBT2iOCfCQgtd jRBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MBFvaiC9HPUxDYn9mI/RWJII1rG7bgB9MV0/lYAgXVI=; b=O59yytgJwiwj2rEUo2klEwFNovoGlaQizl+kZcj6uFS3S7hZESUrk9HaMwL/2nQLNM gZJ+pTpO0CenTILrSb32PKgECXVDsbv56OxfdhS3ODphCPSfV86NSoDFmUKuk2tpkMZx wH7gaJqtb7dhdMWJUG1r04lMhSnmJHLY+caIQrm0C0Czf7sjSbqBPuOEj8tLa5ocSxmz J4MNIL+jFjxrro8+wJW4hmUzX0QrIomKmt37RmRtCiEfA6a120zf+GNII/498KkI6f00 7OCyK+/4tYDBjslsIojs0t9Q3vI9EjF0x7m0ciomaGOpyQPHdEGHQh7PJt0/FpbfRjtd 9Z9A== X-Gm-Message-State: AOAM532bO3gwX8NJ+qn53qYk3Y7FAjzfG2B9nTkdDz9eZHkSe+ZojEKv lkE7nalGpGw6YhZTnp5Jo1Z09Q== X-Received: by 2002:a7b:c395:: with SMTP id s21mr26434020wmj.164.1624888723068; Mon, 28 Jun 2021 06:58:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d12sm12047627wri.77.2021.06.28.06.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jun 2021 06:58:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/18] target/arm: Implement MVE vector shift right by immediate insns Date: Mon, 28 Jun 2021 14:58:25 +0100 Message-Id: <20210628135835.6690-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210628135835.6690-1-peter.maydell@linaro.org> References: <20210628135835.6690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the MVE vector shift right by immediate insns VSHRI and VRSHRI. As with Neon, we implement these by using helper functions which perform left shifts but allow negative shift counts to indicate right shifts. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 12 ++++++++++++ target/arm/translate.h | 20 ++++++++++++++++++++ target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ target/arm/mve_helper.c | 7 +++++++ target/arm/translate-mve.c | 5 +++++ target/arm/translate-neon.c | 18 ------------------ 6 files changed, 72 insertions(+), 18 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 8cd7c6a0d8a..288a8faf4e8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -360,6 +360,10 @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) @@ -375,3 +379,11 @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index e2f056c32c2..4b5db937ef3 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -161,6 +161,26 @@ static inline int times_2_plus_1(DisasContext *s, int x) return x * 2 + 1; } +static inline int rsub_64(DisasContext *s, int x) +{ + return 64 - x; +} + +static inline int rsub_32(DisasContext *s, int x) +{ + return 32 - x; +} + +static inline int rsub_16(DisasContext *s, int x) +{ + return 16 - x; +} + +static inline int rsub_8(DisasContext *s, int x) +{ + return 8 - x; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) != 0; diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 183eb731d2b..8be04589a6c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -64,6 +64,18 @@ @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 +# Right shifts are encoded as N - shift, where N is the element size in bits. +%rshift_i5 16:5 !function=rsub_32 +%rshift_i4 16:4 !function=rsub_16 +%rshift_i3 16:3 !function=rsub_8 + +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ + size=0 shift=%rshift_i3 +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ + size=1 shift=%rshift_i4 +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ + size=2 shift=%rshift_i5 + # Vector loads and stores # Widening loads and narrowing stores: @@ -298,3 +310,19 @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w + +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w + +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w + +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w + +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 285c8b56f78..ac720c9ee05 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1229,6 +1229,10 @@ DO_VADDV(vaddvuw, 4, uint32_t) DO_2SHIFT(OP##b, 1, uint8_t, FN) \ DO_2SHIFT(OP##h, 2, uint16_t, FN) \ DO_2SHIFT(OP##w, 4, uint32_t, FN) +#define DO_2SHIFT_S(OP, FN) \ + DO_2SHIFT(OP##b, 1, int8_t, FN) \ + DO_2SHIFT(OP##h, 2, int16_t, FN) \ + DO_2SHIFT(OP##w, 4, int32_t, FN) #define DO_2SHIFT_SAT_U(OP, FN) \ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ @@ -1240,6 +1244,9 @@ DO_VADDV(vaddvuw, 4, uint32_t) DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) DO_2SHIFT_U(vshli_u, DO_VSHLU) +DO_2SHIFT_S(vshli_s, DO_VSHLS) DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index fc8a2da6e1f..4030ee07f0d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -888,3 +888,8 @@ DO_2SHIFT(VSHLI, vshli_u, false) DO_2SHIFT(VQSHLI_S, vqshli_s, false) DO_2SHIFT(VQSHLI_U, vqshli_u, false) DO_2SHIFT(VQSHLUI, vqshlui_s, false) +/* These right shifts use a left-shift helper with negated shift count */ +DO_2SHIFT(VSHRI_S, vshli_s, true) +DO_2SHIFT(VSHRI_U, vshli_u, true) +DO_2SHIFT(VRSHRI_S, vrshli_s, true) +DO_2SHIFT(VRSHRI_U, vrshli_u, true) diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index f915f70970b..a45616cb631 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -33,24 +33,6 @@ static inline int plus1(DisasContext *s, int x) return x + 1; } -static inline int rsub_64(DisasContext *s, int x) -{ - return 64 - x; -} - -static inline int rsub_32(DisasContext *s, int x) -{ - return 32 - x; -} -static inline int rsub_16(DisasContext *s, int x) -{ - return 16 - x; -} -static inline int rsub_8(DisasContext *s, int x) -{ - return 8 - x; -} - static inline int neon_3same_fp_size(DisasContext *s, int x) { /* Convert 0==fp32, 1==fp16 into a MO_* value */