| Message ID | 20211218194250.247633-9-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: vector improvements | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > AVX512VL has VPSRAVQ, and > AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++-------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 316e550b38..7b9302fcc2 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -418,9 +418,13 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) > #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) > #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) > #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) > +#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) > #define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) > +#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) > +#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > +#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) > #define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) > #define OPC_VZEROUPPER (0x77 | P_EXT) > @@ -2742,16 +2746,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, > OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 > }; > static int const shlv_insn[4] = { > - /* TODO: AVX512 adds support for MO_16. */ > - OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ > + OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ > }; > static int const shrv_insn[4] = { > - /* TODO: AVX512 adds support for MO_16. */ > - OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ > + OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ > }; > static int const sarv_insn[4] = { > - /* TODO: AVX512 adds support for MO_16, MO_64. */ > - OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 > + OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ > }; > static int const shls_insn[4] = { > OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ > @@ -3242,9 +3243,24 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) > > case INDEX_op_shlv_vec: > case INDEX_op_shrv_vec: > - return have_avx2 && vece >= MO_32; > + switch (vece) { > + case MO_16: > + return have_avx512bw; > + case MO_32: > + case MO_64: > + return have_avx2; > + } > + return 0; > case INDEX_op_sarv_vec: > - return have_avx2 && vece == MO_32; > + switch (vece) { > + case MO_16: > + return have_avx512bw; > + case MO_32: > + return have_avx2; > + case MO_64: > + return have_avx512vl; > + } > + return 0; > case INDEX_op_rotlv_vec: > case INDEX_op_rotrv_vec: > return have_avx2 && vece >= MO_32 ? -1 : 0;
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 316e550b38..7b9302fcc2 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -418,9 +418,13 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) +#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) #define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) +#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) +#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) +#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) #define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VZEROUPPER (0x77 | P_EXT) @@ -2742,16 +2746,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 }; static int const shlv_insn[4] = { - /* TODO: AVX512 adds support for MO_16. */ - OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ + OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ }; static int const shrv_insn[4] = { - /* TODO: AVX512 adds support for MO_16. */ - OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ + OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ }; static int const sarv_insn[4] = { - /* TODO: AVX512 adds support for MO_16, MO_64. */ - OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 + OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ }; static int const shls_insn[4] = { OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ @@ -3242,9 +3243,24 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: - return have_avx2 && vece >= MO_32; + switch (vece) { + case MO_16: + return have_avx512bw; + case MO_32: + case MO_64: + return have_avx2; + } + return 0; case INDEX_op_sarv_vec: - return have_avx2 && vece == MO_32; + switch (vece) { + case MO_16: + return have_avx512bw; + case MO_32: + return have_avx2; + case MO_64: + return have_avx512vl; + } + return 0; case INDEX_op_rotlv_vec: case INDEX_op_rotrv_vec: return have_avx2 && vece >= MO_32 ? -1 : 0;
AVX512VL has VPSRAVQ, and AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-)