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[209.51.188.17]) by mx.google.com with ESMTPS id n138si1085104ybf.39.2022.01.06.02.49.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:49:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:60466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QKk-0007vZ-4o for patch@linaro.org; Thu, 06 Jan 2022 05:49:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDX-0007hT-LG for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:59 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:42329) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDQ-0004ie-Hz for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:58 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MlwBf-1medty3FQp-00ixdp; Thu, 06 Jan 2022 11:41:45 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 10/27] target/alpha: Implement prctl_unalign_sigbus Date: Thu, 6 Jan 2022 11:41:20 +0100 Message-Id: <20220106104137.732883-11-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:/w194w6AUFk/pPGKVSE8+c/8Eou0scAsl6irsRgodjQ0NHtE7Sn H6X4R/3oSwy8U58hfJI6bCsN4GuhgyvjQ76dS7EbowUL9jngnRVTrjRRe9+lwpOpKPUZqNn H8dVZReDy+uNSHeRn38izaZW99+gK+U/TqfzqtfxZcCGtLuFBLNB8gREj0EYcWqt1O3AN2X /8z0L4ZkJ8fudUyA7cQ+g== X-UI-Out-Filterresults: notjunk:1;V03:K0:oQS3X5SDv0Q=:SWezH0zMpSpoBB0lf3ODxd E8O8jS9XoSgjzO1pc3FRg3IfX1s6mQU+O54ffQn3BQ2SFoUIUXCnVU6GHGp0XN9JD+/WWTuz9 BPDg/3eE8USmYChEWNHiu8/3zV3hxeQe4y7sAEnDM1xMuoQb+ieIiaDDG3xvQmoqDnKEB2f27 p/MuvkXrmglbhin9HTLoreeexCswl0sH++ORmLfXoQ/fH2OObuNivdP7VbKR9/PcU0GTiO23g D8ufBSigI0zaz1rSZrbwaQRKM5FgRflF8Dn/7pVIwV0snclGctDXRkqDhHxg46Y/v5qkglK6g UJMcQIng1VqRRoTFwKVtJkDtp7VshTYecAx1r+kZW43zTcrZ3lT/tNXoDSe02t+y1PGNcmGBn Gr66cuw6OH/ejVW0mAQVGD0bXdh/mcW3WV3VV49EexlD5W8NkIZ9r/d80m5LOeTy+AEW2i8db a+Iz5e+nWeFegRVkk2ONEQYhsVgVGqVW4A0h82uzLULX/ZSfr2ctEM1DbeDIcGHLoqRAejBQN bw/cPMhO54Mpr5pMTR8KzYZb24ny9HLDkDRflu8jqAAY/bDxPUZA2oLPVVN4xI7dtf7jX38wy bDh5v8azkIgLBuemLCitO47B2L1bIuv4b9nSxMia+cpVncd9EGE5WT5vrIwr59+ZhEMhzuJyW /cdmFLnmL5a0W39y1elk14LHn4+iVo6HO4G+zZeqOG6EV5j3mIW2ACpCiPlkjYP3PXfE= Received-SPF: none client-ip=212.227.126.131; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211227150127.2659293-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/alpha/target_prctl.h | 2 +- target/alpha/cpu.h | 5 +++++ target/alpha/translate.c | 31 ++++++++++++++++++++++--------- 3 files changed, 28 insertions(+), 10 deletions(-) diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h index eb53b31ad554..5629ddbf39cd 100644 --- a/linux-user/alpha/target_prctl.h +++ b/linux-user/alpha/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index afd975c87801..e81921150392 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,6 +383,8 @@ enum { #define ENV_FLAG_TB_MASK \ (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) +#define TB_FLAG_UNALIGN (1u << 1) + static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; @@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif } #ifdef CONFIG_USER_ONLY diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a4c3f43e720a..208ae5fbd50d 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext; struct DisasContext { DisasContextBase base; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#else uint64_t palbr; #endif uint32_t tbflags; @@ -68,6 +70,12 @@ struct DisasContext { TCGv sink; }; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Target-specific return values from translate_one, indicating the state of the TB. Note that DISAS_NEXT indicates that we are not exiting the TB. */ @@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx) static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); tcg_temp_free_i32(tmp32); } @@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv tmp = tcg_temp_new(); - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); tcg_temp_free(tmp); } @@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); tcg_temp_free_i32(tmp32); } static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) { - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else if (!locked) { + op |= UNALIGN(ctx); } dest = ctx->ir[ra]; @@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } @@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) { TCGv tmp = tcg_temp_new(); gen_helper_g_to_memory(tmp, src); - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); tcg_temp_free(tmp); } @@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) { TCGv_i32 tmp32 = tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); - tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL); + tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); tcg_temp_free_i32(tmp32); } static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) { - tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ); + tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx)); } static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16, @@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16, tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); if (clear) { tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + op |= UNALIGN(ctx); } src = load_gpr(ctx, ra); @@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) #ifdef CONFIG_USER_ONLY ctx->ir = cpu_std_ir; + ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->palbr = env->palbr; ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);