From patchwork Thu Jan 6 10:41:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 530346 Delivered-To: patch@linaro.org Received: by 2002:ad5:544f:0:0:0:0:0 with SMTP id a15csp1064954imp; Thu, 6 Jan 2022 02:51:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxTpfEoRSc3agJQQ/Ti3lrcOJAagdioEZThxDcRs++2ODwbo5uYKokdQnztfJ1dqqh6711t X-Received: by 2002:a5b:552:: with SMTP id r18mr71140565ybp.30.1641466315716; Thu, 06 Jan 2022 02:51:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1641466315; cv=none; d=google.com; s=arc-20160816; b=peQWoFOub7V743qQ20oALlKnBWEgpqnFP//u3hEFwFRZ/QiGB1PhYtKcnCVB6MTXCL 0vy2N5wXLIHxExurNucoT9KWvu8Hz6QSgxZ1MwsZvmpkUOvba6YpAVA8jbjvaTFTPAmK IagcgXHZtljO6libZS/hSJEntDsczDK+L5BiAMc8Isd9U52avEcSRy2rpU6dpN54leqh u8HkQ/KsMSqWLnaFaQ3IDSlZT/s6vmgLta/hQvlO8wAvex7jl3nqGI9wgxfSxPMbK+NE tQsDA6q+hmKq4aGDM5ZOBCCaEdQWumUXYKIwqisr8hRzddUmBGGNcvXDtYKxadWQb4ZU a62Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=4QxM044tHsEgv6L2gXumiIaiYcBO+LPIeCtk5Aq/s7Y=; b=VBtoqCW9ClMsePDG9BPAj3rDBOs/mbBMHwE3Gm5WDLevUloIZbUvwGnZt+IRfLfZhL YKopD+qZCF6EtmqcOcvKjt/P6jL4iO0yPqW47VypWhSpu4SL3oSjb4Z5NZf2mcapjWjJ rVKTa6WGmGp6hXOr/GCVNl8BJeX1Z3y5GYn6Kfh4B9i4M145//zwyfsqgxdi4PUCvne2 pSuZuT12oNfkEWbTYrlRRyvMtWndmWHrCa/6KBPD9ZZPaN23pFAP/tRlIgawKKb/p9Go ENWaTMBFlme2v5H2Ms2wkvaH1nxYv4gvxy68KuFlkB5k6JZVVJVLEhy1QsirsvUKEaSf Dcnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 198si1142789ybe.639.2022.01.06.02.51.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jan 2022 02:51:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:39488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5QN9-0004WR-3R for patch@linaro.org; Thu, 06 Jan 2022 05:51:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDV-0007dX-Nc for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:57 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:34251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5QDO-0004ii-Q9 for qemu-devel@nongnu.org; Thu, 06 Jan 2022 05:41:57 -0500 Received: from quad ([82.142.12.178]) by mrelayeu.kundenserver.de (mreue009 [212.227.15.167]) with ESMTPSA (Nemesis) id 1Mgvj3-1mT5C30ruv-00hNCZ; Thu, 06 Jan 2022 11:41:46 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Subject: [PULL 11/27] target/hppa: Implement prctl_unalign_sigbus Date: Thu, 6 Jan 2022 11:41:21 +0100 Message-Id: <20220106104137.732883-12-laurent@vivier.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220106104137.732883-1-laurent@vivier.eu> References: <20220106104137.732883-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:kiwqWioa8pwH62vt2bj2DK8vZUodcrthSFww0+yA4gGf7F37kT7 Scm4mzJPzGjTU7zWY8HhnkDwdop+QIjYtN69i+X35I+AJpRXy8KEu9LS+uSWVzSP4KTsu5z us69Oz+Kemk2mn4tomo3Gx/tDJJ19Ybh/VuNFcZ7B0F4sU9APturR7XeeIAP14qLncxZhQ6 dI0peWLWzOz6xyPqvH1Aw== X-UI-Out-Filterresults: notjunk:1;V03:K0:9KTJbbrXwsY=:U0o8JBZbyFi+M/6JHRuTUa KfqJPaWY9AggjFa71hQYg5QVIRyOstHiznM7PZGrpp0Lc5wLoslyyFEOipRCiNNPTf3PDau5c t/+Mr7jf6HDi8BXeigWOwLXEXCwJ6GxOGAQp5y8PDsNuAVmA5DxaBeHb06dq0cJanov0zVv38 ctPcCAurv3J91A8NpCnTB+DCzX1E/UsPtbPlmn2+5rLXIn50Wo6KQBVCx2IGseHlKi74dndpB uDWSI6XLwIgRi7QWkcK3IMvWmGf4lcZ3Rv43DydyDGf1Tbrrh4O/D4e5/CBG8obvFqydA0K3f ModusbRllON/yYkGsQlufvTxQkxkrHkBFPPIPi6/8KUBQe3znbkXAzQ5pUO8rubNBoBIgTofu DydYZje8DZduWke6bSLj6koQy4Y86VsPaRWWOBfRi3ZJ/jhcUWuCuKu6c4gZjuY9kJrLkXiLU 89awLaolkmdbJC1ooEAv0yrPqwqMmUkEPM7h6wJLUQOQqQ9fR94APU3gK7PXc1Tf3EIpFl2gj lgIn1iRqAARcKHt8m2JkTy/G/aJFOIV5gAMlmGR1pliBOpouA1WnsXMSgA+mKOy0uAVl6N5kY p3m9JJhuoB80KNaUoPoimMnOFyL6q9+aMj/UKGdzTa8tiiAUWJFrSbqIbqIdJEyyU2MI8uNyX hsI1/wHoZ0voSiN29NscXm5QYo08ZBGctpXlHT3tl0lvVYwuuDUPknPBy1b2aRDch0pE= Received-SPF: none client-ip=212.227.126.130; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier Message-Id: <20211227150127.2659293-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/hppa/target_prctl.h | 2 +- target/hppa/cpu.h | 5 ++++- target/hppa/translate.c | 19 +++++++++++++++---- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h index eb53b31ad554..5629ddbf39cd 100644 --- a/linux-user/hppa/target_prctl.h +++ b/linux-user/hppa/target_prctl.h @@ -1 +1 @@ -/* No special prctl support required. */ +#include "../generic/target_prctl_unalign.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 294fd7297f91..45fd338b02f8 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. +/* + * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the * same value. */ #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 +#define TB_FLAG_UNALIGN 0x400 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, target_ulong *cs_base, @@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *pc = env->iaoq_f & -4; *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 952027a28e12..a2392a1b64a4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -274,8 +274,18 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + +#ifdef CONFIG_USER_ONLY + MemOp unalign; +#endif } DisasContext; +#ifdef CONFIG_USER_ONLY +#define UNALIGN(C) (C)->unalign +#else +#define UNALIGN(C) 0 +#endif + /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ static int expand_sm_imm(DisasContext *ctx, int val) { @@ -1475,7 +1485,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1493,7 +1503,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1511,7 +1521,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -1529,7 +1539,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx == MMU_PHYS_IDX); - tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); + tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } @@ -4107,6 +4117,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);