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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/33] target/nios2: Implement CR_STATUS.RSIE Date: Mon, 7 Mar 2022 21:19:51 -1000 Message-Id: <20220308072005.307955-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Without EIC, this bit is RES1. So set the bit at reset, and add it to the readonly fields of CR_STATUS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 1 + target/nios2/cpu.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 7faec97d77..b418deec4c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -108,6 +108,7 @@ FIELD(CR_STATUS, IL, 4, 6) FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) +FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_PIE (1u << R_CR_STATUS_PIE_SHIFT) #define CR_STATUS_U (1u << R_CR_STATUS_U_SHIFT) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbcb4da737..ed7b9f9459 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -59,9 +59,9 @@ static void nios2_cpu_reset(DeviceState *dev) #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->status = CR_STATUS_U | CR_STATUS_PIE; + env->status = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->status = 0; + env->status = CR_STATUS_RSIE; #endif } @@ -109,6 +109,7 @@ static void nios2_cpu_initfn(Object *obj) WR_REG(CR_BADADDR); /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING);