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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y15-20020a05600015cf00b00203e324347bsm6316599wry.102.2022.03.18.06.23.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Mar 2022 06:23:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF Date: Fri, 18 Mar 2022 13:23:01 +0000 Message-Id: <20220318132306.3254960-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220318132306.3254960-1-peter.maydell@linaro.org> References: <20220318132306.3254960-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Connect the ZynqMP CRF - Clock Reset FPD device. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Francisco Iglesias Reviewed-by: Luc Michel Signed-off-by: Edgar E. Iglesias Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 0552ba18b41..7938f223a4a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -39,6 +39,7 @@ #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-zynqmp-efuse.h" #include "hw/or-irq.h" +#include "hw/misc/xlnx-zynqmp-crf.h" #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -124,6 +125,7 @@ struct XlnxZynqMPState { XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; qemu_or_irq qspi_irq_orgate; + XlnxZynqMPCRF crf; char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 47324cdc441..f4575eea7fa 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -52,6 +52,9 @@ #define QSPI_DMA_ADDR 0xff0f0800 #define NUM_QSPI_IRQ_LINES 2 +#define CRF_ADDR 0xfd1a0000 +#define CRF_IRQ 120 + /* Serializer/Deserializer. */ #define SERDES_ADDR 0xfd400000 #define SERDES_SIZE 0x20000 @@ -280,6 +283,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); } +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); + sbd = SYS_BUS_DEVICE(&s->crf); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, CRF_ADDR); + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -684,6 +699,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) xlnx_zynqmp_create_bbram(s, gic_spi); xlnx_zynqmp_create_efuse(s, gic_spi); + xlnx_zynqmp_create_crf(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {