From patchwork Fri Apr 8 14:15:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 558826 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp377565map; Fri, 8 Apr 2022 07:34:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPQvXV7iyLEFrjhQMM73MPZvKOj95MTRJ2YhZQlHAPBgOLkE7BQzxlB+LGZMCBNQHiDQBb X-Received: by 2002:a81:2f12:0:b0:2eb:d54c:6abb with SMTP id v18-20020a812f12000000b002ebd54c6abbmr5176564ywv.123.1649428464087; Fri, 08 Apr 2022 07:34:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649428464; cv=none; d=google.com; s=arc-20160816; b=AyZilVMAhcbrX5lW7hEOAYZAkW2Ramh+ntiIQxORp7UJt6ethpdKsyUjP51ZqIM76U oboD5/qEYF1x5+Bbxneza4GDRYFV5/zlriSUB8BaWxDclqgv957TBiZFvZQsgaZRoh+/ k5k+lwbdlfzzKK6fPLMPGliK+cCV19QfJNfBqwcUpUMsPfNj3kMpYS+SEF/jh2lmdBWs mDqSwwe/w9gWDzCOyPkkPbmHKlpz9x9d+MrQ9AgtlTPfNqdGtyOwZK7VQaL3k5QBxkI/ aSOLYc1mgbqP04c6zY84GosHcifM1JOxtN0ObbiaqMPa8e2KWdMFuQnici8P+xJmHabM H9jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c2w8hD7BvI/mrPbeJHM/ddfGPpF2hd8m8r56TLjlSxo=; b=1Ku+mloazAWX2qEr9qpo4qv9FWMZA39ulbT4Wpfbt+s+H2OTjwJDSxKqDR4qkkrMp9 7sqPEX4YO75uCm5JNA1j/zOUorpkQVEplUCwtkMNb+sXKIk+wnbEd46UCjlETvJH/ks4 ahMM7YdZGZV64BbNU3pQjU4MjjvCvemKzP8928c23eBbSQKsbetRhyIuVqcfqcZwUn8V jk9RL9wBOYv1EI8jVFKasGugKphVaTgW+3h6oDLHaHkMx+76hUfKrry3puu/v9aACl31 gs10l1R761SpuOtZFwjYJ5rJQxPbHDbT/+M00VAr3v4uX5x155+XQXJXH8Pht9fAf6GY dgwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=McqFH8HA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k1-20020a812401000000b002e5bb9dc9casi521701ywk.83.2022.04.08.07.34.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Apr 2022 07:34:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=McqFH8HA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncpgt-0008UJ-JS for patch@linaro.org; Fri, 08 Apr 2022 10:34:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncpPS-00075Z-BV for qemu-devel@nongnu.org; Fri, 08 Apr 2022 10:16:22 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:47033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncpPP-0002Mx-2k for qemu-devel@nongnu.org; Fri, 08 Apr 2022 10:16:20 -0400 Received: by mail-wr1-x42c.google.com with SMTP id v2so2198984wrv.13 for ; Fri, 08 Apr 2022 07:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c2w8hD7BvI/mrPbeJHM/ddfGPpF2hd8m8r56TLjlSxo=; b=McqFH8HAyOz3+0xfW01DCj9eees7vq1ysV+8HonEZDNfQLIHoqcwjsRdJR2PtPrYj2 HCwTHqUW+TUjWqmZHfPvS8ghv3EUcQNVS7KdI8Rk5NmCOsyRCUxBv5W2NEmy5nz5QXQf 9gyOeYtJnH+ll/5aUgYsaDcjzPxPzJI4El4ACLz1N0QJeUHRrbvEyhIcY+63Rmpxm37N Pg01Qj9hDUYi0JDt3HIbR7CqoeuQ7Hg3pDV6nmeDsmnER6x4hkmXGPPKTmd75eKe2SY8 I6NsPZG+CrQrH5L+KGsqUIlDxz2zyA42K7kpIh6hKkKSVng94rgvIc/8tXQ6BDo0s8xC spiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c2w8hD7BvI/mrPbeJHM/ddfGPpF2hd8m8r56TLjlSxo=; b=Z8MZx0KIYwm2NXtPcjUM21tcG5+8gVlsBRV3ICquX8iHKMgyoti8KoHZ6uAV1GmNWA XbxOfvR2OeNYZlEjziomlKrJabdaVh/bLqT0R4A3E+FyvqDC3eZP8PR8EVtOl+bHXu8t OquXq43Y6q3kCr8ldLo7y29ZswlbKwjroF1qF9q8HD7DpGLSNSCkpiKSdbkEwFBanKHH Lnm070zEn6f+jkGL25U4WoQ+tFKSrifqT5YrFjX1djyMCTb9lDyRtqyiWMZmLXC7S8OB Ko8rpGbGbmwQi+wuaF7lyeiabsmYL3E9wActD/eTgB6z08OQS+98Vs+XuFtZZBpD30a3 LAXg== X-Gm-Message-State: AOAM533kzxXMJwxYf4qTb9eWlKzljNU0732GFrR13NS7SAMlIz4fRJKe BNfjU+V7eiwcimsMLNrVZNhvVw== X-Received: by 2002:a05:6000:178c:b0:204:648:b4c4 with SMTP id e12-20020a056000178c00b002040648b4c4mr14519912wrg.219.1649427377731; Fri, 08 Apr 2022 07:16:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 26/41] hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Date: Fri, 8 Apr 2022 15:15:35 +0100 Message-Id: <20220408141550.1271295-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The maintenance interrupt state depends only on: * ICH_HCR_EL2 * ICH_LR_EL2 * ICH_VMCR_EL2 fields VENG0 and VENG1 Now we have a separate function that updates only the vIRQ and vFIQ lines, use that in places that only change state that affects vIRQ and vFIQ but not the maintenance interrupt. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index f11863ff613..d627ddac90f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -543,7 +543,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); return; } @@ -588,7 +588,7 @@ static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, write_vbpr(cs, grp, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -615,7 +615,7 @@ static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, ICH_VMCR_EL2_VPMR_LENGTH, value); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -682,7 +682,7 @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2452,7 +2452,7 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; - gicv3_cpuif_virt_update(cs); + gicv3_cpuif_virt_irq_fiq_update(cs); } static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)