From patchwork Sun Apr 17 17:43:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 562831 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1859493map; Sun, 17 Apr 2022 11:03:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyr9u5tyd9sM4vVn+UAGVBTC1qPKOvcI4Hb4EwoizjKqinHUro4V8wtrOiOV1Ym36HS5dTR X-Received: by 2002:ac8:5948:0:b0:2f2:104:8de5 with SMTP id 8-20020ac85948000000b002f201048de5mr427008qtz.499.1650218628498; Sun, 17 Apr 2022 11:03:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650218628; cv=none; d=google.com; s=arc-20160816; b=a+mhPYlx7lOzdoz29IJO0xiZKhbRqSjCNZF3diB3LR9wNYO+C0K+A50KmhKJ22wmdM 3AoWkn+I6Wqo6yMP8AClQCxzXP5B0ZFfhklRsaHujwnFUfFOOX25Ux7Yfomr3b4x0Ces 6luBciQVuvD2sHWngs4jxrs3wgLSn+q4M18v8eBd+REaWECL9L4OrEW9Hq9awhp/gkUv 9JL2P+S1qjEs6u6YjOb6LR+zulbA9p88TID6l7TiAyhqb41buCHfGcmEvWwzb+ePyYmS nArnPS+35dSiaAtv1GyWUdrlguUwdH/+/khEgyKxjktu9Aq6PV5Lh4NIdd0lmiCH9DLN fdhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=LbXuwEpQ2iNRoH8RoIaz2x7xsI9rBaxEkOQSf6AUYt3ocPa3oHzQpuogAaQXiguvLs h5TkIVddnAnYE9u8Hc6mvmmg15m5YHvYpZslOOTetl1gWQ03s+cF/+l/Oh9ijoDPFQhO iDY766RbpD7lumKhqmj64jSehZ0rruJniu28dNjEcef4fan0dfx2uQQrQgJpf/zYTfLx 0N7Kf3xK4kzNwZ4mYsccvidNzoRa9hLFe2YEHd+SoPeLyh+LFStQuVef+ZJBHOzCVhQl KsDsUqBzFlxC/zaUZvdmZfsG1VgCEqc7Xc90sj2vt5OJeBJRB5g5/Rh1OUB4w9Xop1/R 5UvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PDXnRxqp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d23-20020a05620a159700b0069c437e5737si2205167qkk.243.2022.04.17.11.03.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Apr 2022 11:03:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PDXnRxqp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9FU-00021n-2E for patch@linaro.org; Sun, 17 Apr 2022 14:03:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x0-0000fb-AS for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:43 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:33601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wx-0003Hb-IO for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:42 -0400 Received: by mail-pg1-x534.google.com with SMTP id k14so14986489pga.0 for ; Sun, 17 Apr 2022 10:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=PDXnRxqpB6Ja5X6pHmUS58KPdyU9sgvY3ljJ1wuYioD3iMjqxhl1US2Siw/MnLHRmm KDWsbWAByfc0AtQ2C1aieJm4zbxOClH7c6OOt2y8hBoeuNI0AlJT/MJEn8NEJFcBBfYB ao0RyFRr/Tp/D12Gw1gAw51lT/yp25XR4606YZEPIGyqoW01/vRbTW5JF2PywahmTWy5 J4WKLJ1XfO6g5nR1YCgSllkqelxOc+f/5xBnc1e1RBLHICicd0oyHooWbfI+COkEDmyX mfhDYthyZ8dYoZmEEHM/HOnYha9srcbSTxv5tRCM6PP+BS91cz7u9OhO+jtZcxEUl280 NJjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=k2eDWJM8M6UHwvqZTclmRKPqOQ+viX2RmHSF+RUwB4QmrFODSarlsqeFoLOs0Itjd9 dMTMnfLaWpHF4jWHLW4S4WqYFyYKXzvc7zNFoaQiCsPjdoLF1xEzzood9SK2mmXRtJkV GCVqUvz/TD2FVsLzxQ6GRadb3cRVoHBGkdR0XBwco6LYLGy1U4AjNW0fY1rFk86ZwtP4 yi96sT0GjKplDEwZSEMzWtdo3GMGjCNKa3V4cVS8njogtHBJpMl+In7LnHgPD6XfVdCy faRlFaP2IdOyoH+tYVU87sSbKP4GW0rtJcqFUfdt5/ICYTqRweRoK8MrpzVDQ2GKY8G/ dWdw== X-Gm-Message-State: AOAM5302+/e2mD5OOw8hNGbaLv/830O9/QJtdDuonu3Y+KAwgilpzaFW CpCiKepUBJkjf3SCJzgBD3UbgPdLTDg5sw== X-Received: by 2002:a63:4f43:0:b0:39d:96ff:838c with SMTP id p3-20020a634f43000000b0039d96ff838cmr6937937pgl.115.1650217478256; Sun, 17 Apr 2022 10:44:38 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/60] target/arm: Remove fpexc32_access Date: Sun, 17 Apr 2022 10:43:36 -0700 Message-Id: <20220417174426.711829-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is incorrect in that it does not properly consider CPTR_EL2.FPEN. We've already got another mechanism for raising an FPU access trap: ARM_CP_FPU, so use that instead. Remove CP_ACCESS_TRAP_FP_EL{2,3}, which becomes unused. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 ----- target/arm/helper.c | 17 ++--------------- target/arm/op_helper.c | 13 ------------- 3 files changed, 2 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4eb378ede2..e7f669d0a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2806,11 +2806,6 @@ typedef enum CPAccessResult { /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, - /* Access fails and results in an exception syndrome for an FP access, - * trapped directly to EL2 or EL3 - */ - CP_ACCESS_TRAP_FP_EL2 = 7, - CP_ACCESS_TRAP_FP_EL3 = 8, } CPAccessResult; /* Access functions for coprocessor registers. These cannot fail and diff --git a/target/arm/helper.c b/target/arm/helper.c index 47fe790854..60d9233b7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4785,18 +4785,6 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, } } -static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { - return CP_ACCESS_TRAP_FP_EL2; - } - if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_FP_EL3; - } - return CP_ACCESS_OK; -} - static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5098,9 +5086,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, - .type = ARM_CP_ALIAS, - .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), - .access = PL2_RW, .accessfn = fpexc32_access }, + .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, .access = PL2_RW, .resetvalue = 0, diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..2b87e8808b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -691,19 +691,6 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = 3; syndrome = syn_uncategorized(); break; - case CP_ACCESS_TRAP_FP_EL2: - target_el = 2; - /* Since we are an implementation that takes exceptions on a trapped - * conditional insn only if the insn has passed its condition code - * check, we take the IMPDEF choice to always report CV=1 COND=0xe - * (which is also the required value for AArch64 traps). - */ - syndrome = syn_fp_access_trap(1, 0xe, false); - break; - case CP_ACCESS_TRAP_FP_EL3: - target_el = 3; - syndrome = syn_fp_access_trap(1, 0xe, false); - break; default: g_assert_not_reached(); }