diff mbox series

[v3,31/60] target/arm: Name CPSecureState type

Message ID 20220417174426.711829-32-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Cleanups, new features, new cpus | expand

Commit Message

Richard Henderson April 17, 2022, 5:43 p.m. UTC
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h | 7 ++++---
 target/arm/helper.c | 3 ++-
 2 files changed, 6 insertions(+), 4 deletions(-)

Comments

Peter Maydell April 22, 2022, 9:57 a.m. UTC | #1
On Sun, 17 Apr 2022 at 19:21, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
> Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
> is handled in define_one_arm_cp_reg_with_opaque.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpregs.h | 7 ++++---
>  target/arm/helper.c | 3 ++-
>  2 files changed, 6 insertions(+), 4 deletions(-)

Maybe also change the "default" in the switch in
define_one_arm_cp_reg_with_opaque() to "case ARM_CP_SECSTATE_BOTH" ?
Either way,
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fe338730ab..3528c0ebb1 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -133,10 +133,11 @@  typedef enum {
  * registered entry will only have one to identify whether the entry is secure
  * or non-secure.
  */
-enum {
+typedef enum {
+    ARM_CP_SECSTATE_BOTH = 0,       /* define one cpreg for each secstate */
     ARM_CP_SECSTATE_S =   (1 << 0), /* bit[0]: Secure state register */
     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
-};
+} CPSecureState;
 
 /*
  * Access rights:
@@ -268,7 +269,7 @@  struct ARMCPRegInfo {
     /* Access rights: PL*_[RW] */
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
-    int secure;
+    CPSecureState secure;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8b89039667..7c569a569a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8503,7 +8503,8 @@  CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
-                                   void *opaque, CPState state, int secstate,
+                                   void *opaque, CPState state,
+                                   CPSecureState secstate,
                                    int crm, int opc1, int opc2,
                                    const char *name)
 {