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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id p11-20020a17090ad30b00b001cd4989fed3sm1712383pju.31.2022.05.03.12.49.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 12:49:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/74] semihosting: Split out common_semi_has_synccache Date: Tue, 3 May 2022 12:47:47 -0700 Message-Id: <20220503194843.1379101-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220503194843.1379101-1-richard.henderson@linaro.org> References: <20220503194843.1379101-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We already have some larger ifdef blocks for ARM and RISCV; split out a boolean test for SYS_SYNCCACHE. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- semihosting/arm-compat-semi.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index b2816e9f66..6149be404f 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -224,6 +224,12 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs) CPUARMState *env = &cpu->env; return is_a64(env) ? env->xregs[31] : env->regs[13]; } + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + /* Invalid for A32/T32. */ + return !is_a64(env); +} #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -260,6 +266,11 @@ static inline target_ulong common_semi_stack_bottom(CPUState *cs) CPURISCVState *env = &cpu->env; return env->gpr[xSP]; } + +static inline bool common_semi_has_synccache(CPUArchState *env) +{ + return true; +} #endif /* @@ -1103,16 +1114,11 @@ void do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ -#ifdef TARGET_ARM - if (is_a64(cs->env_ptr)) { + if (common_semi_has_synccache(env)) { common_semi_set_ret(cs, 0); break; } -#endif -#ifdef TARGET_RISCV - common_semi_set_ret(cs, 0); -#endif - /* fall through -- invalid for A32/T32 */ + /* fall through */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); cpu_dump_state(cs, stderr, 0);