| Message ID | 20220602214853.496211-40-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Scalable Matrix Extension | expand |
On Thu, 2 Jun 2022 at 23:18, Richard Henderson <richard.henderson@linaro.org> wrote: > > We need SVL separate from VL for RDSVL at al, as well as "et al" > ZA storage loads and stores, which do not require PSTATE.SM. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 12 ++++++++++++ > target/arm/translate.h | 1 + > target/arm/helper.c | 8 +++++++- > target/arm/translate-a64.c | 1 + > 4 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e41a75a3a3..0c32c3afaa 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) > FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) > FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) > FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) > +FIELD(TBFLAG_A64, SVL, 24, 4) Given that both SVE and SME start with an 'S', maybe "SME_VL" would be less prone to confusion? On the other hand, SVL is the architectural name, so maybe that's best. > /* > * Helpers for using the above. > @@ -3337,6 +3338,17 @@ static inline int sve_vq_cached(CPUARMState *env) > return EX_TBFLAG_A64(env->hflags, VL) + 1; > } > > +/** > + * sme_vq_cached > + * @env: the cpu context > + * > + * Return the SVL cached within env->hflags, in units of quadwords. > + */ > +static inline int sme_vq_cached(CPUARMState *env) Same remark as earlier about not needing to put "cached" in the function name. Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 6/7/22 02:58, Peter Maydell wrote: >> @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) >> FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) >> FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) >> FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) >> +FIELD(TBFLAG_A64, SVL, 24, 4) > > Given that both SVE and SME start with an 'S', maybe > "SME_VL" would be less prone to confusion? On the other hand, > SVL is the architectural name, so maybe that's best. Yeah, my first version used SME_LEN, but in the end I thought using the architectural name was best. Just above, there's commentary using the other architectural names "VL" and "NVL". >> +static inline int sme_vq_cached(CPUARMState *env) > > Same remark as earlier about not needing to put "cached" in the function name. Already fixed. :-) r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e41a75a3a3..0c32c3afaa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) +FIELD(TBFLAG_A64, SVL, 24, 4) /* * Helpers for using the above. @@ -3337,6 +3338,17 @@ static inline int sve_vq_cached(CPUARMState *env) return EX_TBFLAG_A64(env->hflags, VL) + 1; } +/** + * sme_vq_cached + * @env: the cpu context + * + * Return the SVL cached within env->hflags, in units of quadwords. + */ +static inline int sme_vq_cached(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, SVL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate.h b/target/arm/translate.h index fbd6713572..1330281f8b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cb78d2354a..c9db12d524 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13874,7 +13874,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el = sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el == 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 40f2e53983..b1d2840819 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14652,6 +14652,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE);
We need SVL separate from VL for RDSVL at al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 12 ++++++++++++ target/arm/translate.h | 1 + target/arm/helper.c | 8 +++++++- target/arm/translate-a64.c | 1 + 4 files changed, 21 insertions(+), 1 deletion(-)