diff mbox series

[PULL,44/55] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset

Message ID 20220609090537.1971756-45-peter.maydell@linaro.org
State Accepted
Commit 87252bdecdafd49f8f4da6244a40415c27053bc3
Headers show
Series [PULL,01/55] target/arm: Declare support for FEAT_RASv1p1 | expand

Commit Message

Peter Maydell June 9, 2022, 9:05 a.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

We don't need to constrain the value set in zcr_el[1],
because it will be done by sve_zcr_len_for_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d2bd74c2ed4..06219441674 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -208,8 +208,7 @@  static void arm_cpu_reset(DeviceState *dev)
                                          CPACR_EL1, ZEN, 3);
         /* with reasonable vector length */
         if (cpu_isar_feature(aa64_sve, cpu)) {
-            env->vfp.zcr_el[1] =
-                aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
+            env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
         }
         /*
          * Enable 48-bit address space (TODO: take reserved_va into account).