From patchwork Fri Jul 8 15:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588536 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp770255mab; Fri, 8 Jul 2022 08:38:09 -0700 (PDT) X-Google-Smtp-Source: AGRyM1u+sOT06TJJou+JnhsgU3E0KbDXw/riKIvvkbt8DyESR70AxIjS/syrRjuMkxrNM7lkgNsi X-Received: by 2002:a0c:b456:0:b0:470:7aff:7e8c with SMTP id e22-20020a0cb456000000b004707aff7e8cmr3063291qvf.53.1657294689485; Fri, 08 Jul 2022 08:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294689; cv=none; d=google.com; s=arc-20160816; b=xThjD5eSaRpQugu4fNgf5eSr5MXdqR8ee6mY1UiKaIGiBLesrTVqbC8Mx5W58/VBFy XOtkcOSGEzf+tIOl5e0gziyxTWQbDSWFNnlEaAjCr0+0N7GnSYtPVWswvyC7L+HR1xAu uw7WKOF5YBC7p1KTwe0FXz7cfdLlS3P2vj9gcKwHqN4cAZcOZuVADptiR2jpw8q3DCbr E4IChhm2NC21LNFniOTE8CG6/5AlRv1FAU2Qyts66aWOkHuJP86nfOrl1w0YfdUxYUGI 2SW75eJ14NGlnvF2bGaFXOWbQsGZwTJw3UD3RodCKLj+eA2FE5DC1HQEzAlFQyE9c8Cu 1/gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=RK6/KlfgY6IuVA1Fy+Oqhn7djbW08gjmDi2e/KuoYA17rI0cqJgILEdRlpyI2Qph1y 49cGtWbPjcU26BHIAZssGlF/W8NGeImUeeKRPE1UcEbnLBS9CSKxPWIGzZn/+xq2qLvZ s5+Dh8Jd1I5redy6YTuymOkS5OHmO39XyUknRUCWa+QuwY5HYicIQeHSQNEZqP0sO3r2 7JJrJRMH4PURWuu64QzEeIvraL7zUWYzp8eXyIuAj2KXbkihO0/r85EXV3gxJjCSxnZe XGyRDlDYySc+NY4dPyz92PAyny2X4drNn5kuCibidUPovN4KZmQv4gYlVHky/YgYWp4l 0NgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TW36E2ZK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id de30-20020a05620a371e00b006a6e38e7574si10438342qkb.500.2022.07.08.08.38.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Jul 2022 08:38:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TW36E2ZK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o9q3R-0000WI-J2 for patch@linaro.org; Fri, 08 Jul 2022 11:38:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o9pjG-00047A-8i for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:14 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:33680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o9pjE-0002PV-HP for qemu-devel@nongnu.org; Fri, 08 Jul 2022 11:17:13 -0400 Received: by mail-pl1-x632.google.com with SMTP id p16so1876497plo.0 for ; Fri, 08 Jul 2022 08:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=TW36E2ZK6c6exLnYdxw9aKW14NSYb0f2AI10Ldr3/CGISt0fY0S91+p76qgATLxcD+ uABJfHIgOAzI5B3eTlX+eKY8TlASbeG53QFanniCX4ZDf+xwWz9uQjZg/wScYCngfqgT 9WZ1aSq1dsAww3W8XN6kGdrIq4VdHnnw5TRYVI4rP3DMLgdVR3BdBniyRLdjD18nhAqA cm4evZW5C77Fzg+0EABpSQP1R+y3ZheiXQATQSBmaq76mRIMTwmevI5EXQQiK3pxn6li TFyo0Lh/hIBc8Vl1n368LG3CD2BXiRqOV7+ix8Tx2c5p9TzuB5x0icMAbvC0izXqFtcn 1nzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=HZ3w6C0+tt9HXP9EV4F7VRaIFVJzhsCyOsmbVWVPjSSW9Bso0yXX57kA1NIq+OKYbs 8Ge42pmisCAzIDe1fmPsfUGAd4xEqXu7DZpb+Hcox2g2QiIqSYWBQVHx4qZvuBZBMGEX NDtXF2Vp+2WgjvhiPjI5pHmAPkXMTDaUf9BSzEYtSmWFV1D91XRabhm+w4j7Loof0UWH xeh8MEG7MS2wbXhWQApQvKaVcA/mbzMr+wiowdI81GMSk8eqoTNEUgFp3eafS0e/DTdB VEPEDlhr+s58hSsgdgs7wAncGpCRPUVLO/ApEW1KC77c5iwyXjLq2fNmZVtbrXJ9TiUd GvJQ== X-Gm-Message-State: AJIora8mSEcTh3V5nxtWou3grSXfmzGfIjejhK8iLLOY2+EGaRwpvi02 Ct4XtVSQ0tihRrSZsLN1ACHzai+DWIvVx96F X-Received: by 2002:a17:902:9a46:b0:16b:f25b:d50 with SMTP id x6-20020a1709029a4600b0016bf25b0d50mr4117137plv.154.1657293431258; Fri, 08 Jul 2022 08:17:11 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 28/45] target/arm: Implement PSEL Date: Fri, 8 Jul 2022 20:45:23 +0530 Message-Id: <20220708151540.18136-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 +++++++++++++ target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95af08c139..966803cbb7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=plus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=0 imm=%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=1 imm=%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=2 imm=%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3 imm=%psel_imm_d diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fd1a173637..24ffb69a2a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7419,3 +7419,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl = vec_full_reg_size(s); + int pl = pred_gvec_reg_size(s); + int elements = vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + dbit = tcg_temp_new_i64(); + didx = tcg_temp_new_i64(); + ptr = tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +}