From patchwork Thu Jul 14 13:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 590382 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp1576292max; Thu, 14 Jul 2022 06:27:36 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t0j0YX17CE/S9ekhGWeKrJUTdgvzlUoOmiT1lmspT0F4JYKuXjpTSUUJSE50uWoVF1Hj4h X-Received: by 2002:a05:620a:458a:b0:6b5:9c24:b24d with SMTP id bp10-20020a05620a458a00b006b59c24b24dmr5634772qkb.369.1657805256612; Thu, 14 Jul 2022 06:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657805256; cv=none; d=google.com; s=arc-20160816; b=nHgKRaXuupCLnPLMyrgDKmP2u9OPCI9AS4F7WCM725b9e62VZNof6u8qN+XrtVa9yv TfVBl1gKHyrwCeJQAy9Z+QT+xA1g32FHxtklSRzJU4I9+roaMjwIK4pqF/ZunZvBKeNg BU1YpdHe5R45wBcSJ+idL9XQWYM4L0CVIehhNFLsKFV+r4xI2IAwB7RnOuqkPpd/hdFj lyonsD+3zedSKufuUMLszmb2TYid13Z/VsP7c0e4uw6ePnC5yG6JD67lNZBl+nZwrQMm VmrenfvYPsazR02KJ001KXaSVyqkGMU7CMof9XhE/o626wnYZgN5DM9EsSbdbQzYbNQl WbEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=Tw67XokyroydgUjuFPR6tb1bFLbOHUZ/u8BKLaQl0MhBfmVrpIjBtIcKHis+79VKAn CxXIAhNYdu97kSBih4H7fh11yLTocmZ6M0ZrB0oo46l3PeVCL6/YIgLOHQ4l+ybVjcoK FlQHJlU2gHQPy/L3VSnqr3Asyp0aVOVux4SRBGgC6Jo1gKEhqIgfQoyckWuB/saSMRi7 SgdZ1GnY3TrrA0+tkPdYhvzjLovCgNsc8jid7OujowBbycf8KOrvsyR4oNUCVOuHyKpH uiYrZ7PY+f+LymUqr9UnpzjAMKDgUYSW9oMus3N8drQ2QJnx+4VZabqj4CFf7jhz5J5q NF7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E1Ogb8AT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jt1-20020a05621427e100b00473a3e622fbsi778979qvb.192.2022.07.14.06.27.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Jul 2022 06:27:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E1Ogb8AT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBysR-0002xa-2m for patch@linaro.org; Thu, 14 Jul 2022 09:27:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oByoC-0002FT-9I for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:12 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oByoA-0004op-Kc for qemu-devel@nongnu.org; Thu, 14 Jul 2022 09:23:11 -0400 Received: by mail-wr1-x435.google.com with SMTP id d16so2533608wrv.10 for ; Thu, 14 Jul 2022 06:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=E1Ogb8ATOmPtoZcZwHIWyu8jm4DPdWr54lFLGgTjP803agCv+IcXOPBNhVxfx/FDcv v4PJfuZQHfTO5s2JdcgTv2SEUmCjepkYyTzMLTgdL2qM49tQ11sgB9X3Z5Fu54Akhs6z 4qFmWrlwa8kp7hoTJE7XKF7MGHYpw4P/frJEv4kDvjC/7yeY5kxfqClRLx0VSPP76JVn 486VDT5WES7g4z+rXCfI7q5n2IZFp1yQhD/pRAYWfIaX/m3kFK0Hy6+GhNPb9crq1zBB FMsBYv+Jf9fS9f+PhzFuV1h7dVIuJVh67lhJ2TG+2DzZ247jt34i1E8VluUrtYnEbaXX Orjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bMOS0wQ3/jAb1bU1b2bDXRVo7/duCbF4KRhimcopz70=; b=Ps6E2W1lg1+80BLjbavDjT2WkbSRGvhaJQx2VDuqvCWprk90oL0cikyHeYHTOPz+Ps UPk7wf+B2HGFK7vrorS5QCCFGKcemHqJu9FPYizdNsSArnizYbhWxB+JySUs7B3snLVI tNlbqmfuh2IsMC8hacg8SZpLh4eIZio9XLC/B/93sZibBdcCsDo9cg4alWzKL8+EVG9b 8EZl9InjCsbew6QOKpR4D/g/M57LYKx0DAF7PxMZukbmJWE7ujQ5oOLFX4bPw2br5cmi dRL0tGpy9UqZ0sIl7taPsEeMU3DoAFLXbhAAy29CPwLkmlUW/fbiAvLcQLLx/e7BZKO+ xSwA== X-Gm-Message-State: AJIora9x3OJ37ET0awaQWYtGbkEiu5q/ckPqaNO+Ca1EP2u5kk6CbPhF fgtApa3bBn7Bs0XRV1q/y6h5MA== X-Received: by 2002:a05:6000:1cc:b0:21d:a352:116b with SMTP id t12-20020a05600001cc00b0021da352116bmr7944120wrx.418.1657804989372; Thu, 14 Jul 2022 06:23:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id k11-20020a7bc40b000000b0039c5cecf206sm1925079wmi.4.2022.07.14.06.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 06:23:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Idan Horowitz Subject: [PATCH 4/7] target/arm: Fix big-endian host handling of VTCR Date: Thu, 14 Jul 2022 14:23:00 +0100 Message-Id: <20220714132303.1287193-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714132303.1287193-1-peter.maydell@linaro.org> References: <20220714132303.1287193-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full set of read/write/reset functions -- the various other TCR cpreg structs used one or another of those strategies, but for VTCR we did not, so on a big-endian host VTCR accesses would touch the wrong half of the register. Use offsetoflow32() in the VTCR register struct. This works even though the field in the CPU struct is currently a struct TCR, because the first field in that struct is the uint64_t raw_tcr. None of the other TCR registers have this bug -- either they are AArch64 only, or else they define resetfn, writefn, etc, and expect to be passed the full struct pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Actually I'm not 100% sure that TTBCR is handled correctly for big-endian hosts. But it's going to go away shortly anyway. --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3d4317c4c85..7eee2007a0e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .type = ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, - .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, + .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .access = PL2_RW,