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([2602:47:d48a:1201:9f9e:e00f:d585:c303]) by smtp.gmail.com with ESMTPSA id k30-20020aa79d1e000000b00574f83c5d51sm6372521pfp.198.2022.11.29.12.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:41:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH for-7.2] target/arm: Set TCGCPUOps.restore_state_to_opc for v7m Date: Tue, 29 Nov 2022 12:41:46 -0800 Message-Id: <20221129204146.550394-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This setting got missed, breaking v7m. Fixes: 56c6c98df85c ("target/arm: Convert to tcg_ops restore_state_to_opc") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1347 Signed-off-by: Richard Henderson Signed-off-by: Evgeny Ermakov Reviewed-by: Philippe Mathieu-Daudé --- The patch is unchanged from the correct suggestion in the issue. If Evgeny would like to reply with his s-o-b, this patch could be commited with updated Author. r~ --- target/arm/internals.h | 4 ++++ target/arm/cpu.c | 6 +++--- target/arm/cpu_tcg.c | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d9121d9ff8..161e42d50f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -185,6 +185,10 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); +void arm_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data); + #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a021df9e9e..38d066c294 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -91,9 +91,9 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } } -static void arm_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) +void arm_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) { CPUARMState *env = cs->env_ptr; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 60ff539fa1..9a2cef7d05 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1035,6 +1035,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, + .restore_state_to_opc = arm_restore_state_to_opc, #ifdef CONFIG_USER_ONLY .record_sigsegv = arm_cpu_record_sigsegv,