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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:18:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 27/40] target/arm: Split out strongarm_class_init Date: Tue, 3 Jan 2023 10:16:33 -0800 Message-Id: <20230103181646.55711-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112f; envelope-from=richard.henderson@linaro.org; helo=mail-yw1-x112f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use an intermediate function to share code between sa1100_class_init and sa1110_class_init. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu_tcg.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 1ef825b39e..c6d50f326e 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -837,21 +837,24 @@ static void ti925t_class_init(ARMCPUClass *acc) acc->reset_sctlr = 0x00000070; } -static void sa1100_class_init(ARMCPUClass *acc) +static void strongarm_class_init(ARMCPUClass *acc) { - acc->dtb_compatible = "intel,sa1100"; set_class_feature(acc, ARM_FEATURE_STRONGARM); set_class_feature(acc, ARM_FEATURE_DUMMY_C15_REGS); - acc->midr = 0x4401A11B; acc->reset_sctlr = 0x00000070; } +static void sa1100_class_init(ARMCPUClass *acc) +{ + strongarm_class_init(acc); + acc->dtb_compatible = "intel,sa1100"; + acc->midr = 0x4401A11B; +} + static void sa1110_class_init(ARMCPUClass *acc) { - set_class_feature(acc, ARM_FEATURE_STRONGARM); - set_class_feature(acc, ARM_FEATURE_DUMMY_C15_REGS); + strongarm_class_init(acc); acc->midr = 0x6901B119; - acc->reset_sctlr = 0x00000070; } static void pxa250_class_init(ARMCPUClass *acc)