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Thu, 5 Jan 2023 19:14:08 -0800 (PST) Received: from toolbox.wdc.com (unknown [10.225.167.28]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4Np7jC1Tr9z1RvTp; Thu, 5 Jan 2023 19:14:07 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Date: Fri, 6 Jan 2023 13:13:17 +1000 Message-Id: <20230106031357.777790-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> References: <20230106031357.777790-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=363443eaf=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 191197853f..2a84c57bec 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -700,9 +700,15 @@ static void tcg_out_addsub2(TCGContext *s, if (cbl) { tcg_out_opc_imm(s, opc_addi, rl, al, bl); tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); - } else if (rl == al && rl == bl) { + } else if (al == bl) { + /* + * If the input regs overlap, this is a simple doubling + * and carry-out is the input msb. This special case is + * required when the output reg overlaps the input, + * but we might as well use it always. + */ tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); - tcg_out_opc_reg(s, opc_addi, rl, al, bl); + tcg_out_opc_reg(s, opc_add, rl, al, al); } else { tcg_out_opc_reg(s, opc_add, rl, al, bl); tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,