From patchwork Tue Jan 10 16:43:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640870 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2855419pvb; Tue, 10 Jan 2023 10:29:22 -0800 (PST) X-Google-Smtp-Source: AMrXdXvSxf+wHuNKPi5AYRjCAsOLtvMJtJ924rmrKYfeeVFxKXIBn0M1HlZ2QjxP2EjOe1Fvu8H6 X-Received: by 2002:ac8:5401:0:b0:39c:da20:616 with SMTP id b1-20020ac85401000000b0039cda200616mr4937639qtq.32.1673375362137; Tue, 10 Jan 2023 10:29:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673375362; cv=none; d=google.com; s=arc-20160816; b=qGCgB0SsZRInUff+XotlCL0f+Uu4HMpByshASX70Tc/QD8KcGTMM96eVBC9CCQfwLc oOf01/LnkRrmBc1iYzTvxXlN2nQataT2GOUdF/lwGOSsKOkYGj6JvwITmXgSf535w03v qlPZgAdbJ4v1NMfUVMqD5RTnOultoPFYKrnh3rnV4541TTBC+5HJYxI22a0GbJXcDtSJ zn3laBIxLu5DdMj28LQbK5hXWV9Bqx+9QFQqRz9YH4GMtSwFTTfmAEonD4f9/xVAKPlc mGKQ2iA02f0aYyrTtKNhDmPSVRP30cKUKk0z2aRvI+d49niGYlN1/akYVChLezyqnzKe b5zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QOYDxSc6OXbzkAgjy4QYJseOLob50f8TeLldg9E4I/c=; b=kVwzjtBaB07hnArAPB2SCHkdxl0U0S7kft55jtsyLoHOGQ6qMrkAMIwnM5SnMtO1eg p837TIRQnJB4/d5KyNCw7WC0AkTEHkwSvwfMgRlS3vEoeA6qVzevfoLIPanLAS/3sw79 k1QYSSOXq6uVLPbO7sAGjJlAdBUQNs3ho1zpJsqI8/vPNEmnhPLFa/ZWPu/wyksowvOU 8aBCUJEWYOs9zePfJ2aw7IclQzVVUQh6ms/3QoNuNGyzgpin5YMtVyTKdjTyUlZRURad EeFm3+nOfbz66oT1aOZyMrxPYJX9AWd7cXWzjWkcNoELyovxlX+vOmpZ4JV/YANBLNTi //gQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KmsiWHbe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s22-20020ac85ed6000000b003a8273b59bfsi6529759qtx.213.2023.01.10.10.29.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Jan 2023 10:29:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KmsiWHbe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHk1-000432-L7; Tue, 10 Jan 2023 11:44:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHjz-00042I-H8 for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:47 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHjx-0006DA-Lc for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:47 -0500 Received: by mail-wm1-x32d.google.com with SMTP id bi26-20020a05600c3d9a00b003d3404a89faso1146169wmb.1 for ; Tue, 10 Jan 2023 08:44:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QOYDxSc6OXbzkAgjy4QYJseOLob50f8TeLldg9E4I/c=; b=KmsiWHbeYo5WOPbJFMJP76T1tNWPGlZ4g1u5VBJ5+WJzyF+11Kam075gcfhp8+kjy6 Z+ypXL8JuBBJWANd+TEay96n4x4on/bo8wo/z2PqGB2ko0+DqWmpIOiIDHSpOk/uEUlv uIWBdVci61nIhC5Cxc0jeuwKV9fUFNC7qDm1uAS5bk+6WEy2+QBKdtU5P3HM0sLDWNtL XG5hVc3aODiZazXjqsmkKSE9ZapAqws+2PMerBdlmxrN5iAmJh5JahFofYd8gU7Mzd1W bb08n47gOplHEYsfyUyPdykU4piOnW534o8kz/hEQR+0xmkdEX3BGLsFz3opZlPxQerd ZJcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QOYDxSc6OXbzkAgjy4QYJseOLob50f8TeLldg9E4I/c=; b=ne78/o8vLuVwXv4Mzx0yZfdBsHlxhflPNIkfdkg2XRk7AbdGK/Qm2STBlquqNBGPb0 FtXdURGUtvYfW3EwnCXsSGBMK9qWL+06UQ4nDc+XP0oTKKt+X59rRXi+X22ZIjec+NU9 OfFScuSp6tsrmRR2LW208Xrxuq0yU3nmktWMyL0kLyNE1SN8CSDu0OHomy4ZLzYgPMNe bP1IEO6Ou4ZrVfdVFZ6g24kkciGtOch2t3HLwlKtP5J5js0Sq3Y4TLuBTotU/okTivrx rvOZYBecVgEROP8ozB6D0SSlFccxQ70/1MWmFX5RAfYyqkSBSa5X3p/alfoyWw235sAd DV0g== X-Gm-Message-State: AFqh2kpNWTW0gOcMyJFYpDK/SGZ6qNR6/BT7pjBgLr2V3kzSyGyaEref t0qbgcX+/arXyTsQW7QMGM9DzmcTim107aFj X-Received: by 2002:a05:600c:4f08:b0:3d9:efd1:214d with SMTP id l8-20020a05600c4f0800b003d9efd1214dmr6194442wmq.25.1673369083044; Tue, 10 Jan 2023 08:44:43 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm20873245wmc.13.2023.01.10.08.44.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:44:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 06/18] target/arm: Move CPU definitions consumed by HW model to "hw/arm/cpu.h" Date: Tue, 10 Jan 2023 17:43:54 +0100 Message-Id: <20230110164406.94366-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230110164406.94366-1-philmd@linaro.org> References: <20230110164406.94366-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Units including "target/arm/cpu.h" can't be built once via meson's softmmu_ss[] source set. Since this header depends on specific definitions such the word size (32 or 64-bit), for ARM such units must go to the per-target arm_ss[]. We want to expose few architectural definitions to hardware models. Expose the ARM architectural definitions used by hardware models, in order to reduce the inclusion of "target/arm/cpu.h". Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu-qom.h | 15 -------------- target/arm/cpu.h | 34 ------------------------------ 3 files changed, 49 insertions(+), 49 deletions(-) diff --git a/include/hw/arm/cpu.h b/include/hw/arm/cpu.h index 0c5d6ca2a8..6758bffe34 100644 --- a/include/hw/arm/cpu.h +++ b/include/hw/arm/cpu.h @@ -25,4 +25,53 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +enum QemuPsciConduit { + QEMU_PSCI_CONDUIT_DISABLED = 0, + QEMU_PSCI_CONDUIT_SMC = 1, + QEMU_PSCI_CONDUIT_HVC = 2, +}; + +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 + +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + #endif diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b98904b6bc..d37037e214 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -68,19 +68,4 @@ void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); void arm_gt_hvtimer_cb(void *opaque); -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 52ac99cad3..ab6fdecf48 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,21 +72,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -107,12 +92,6 @@ enum { #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts @@ -160,13 +139,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -3323,12 +3295,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); -enum { - QEMU_PSCI_CONDUIT_DISABLED = 0, - QEMU_PSCI_CONDUIT_SMC = 1, - QEMU_PSCI_CONDUIT_HVC = 2, -}; - #ifndef CONFIG_USER_ONLY /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)