| Message ID | 20230223204342.1093632-11-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | {tcg,aarch64}: Add TLB_CHECK_ALIGNED | expand |
On 23/2/23 21:43, Richard Henderson wrote: > Allow the target to set tlb flags to apply to all of the > comparators. Remove MemTxAttrs.byte_swap, as the bit is > not relevant to memory transactions, only the page mapping. > Adjust target/sparc to set TLB_BSWAP directly. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > include/exec/cpu-defs.h | 3 +++ > include/exec/memattrs.h | 2 -- > accel/tcg/cputlb.c | 5 +---- > target/sparc/mmu_helper.c | 2 +- > 4 files changed, 5 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ef10c625d4..53743ff3f2 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -170,6 +170,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1bd7b6c5ca..5300649c8c 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -45,8 +45,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cc98df9517..a90688ac30 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1168,14 +1168,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a98dd0abd4..fa58b4dc03 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap = true; + full->tlb_fill_flags |= TLB_BSWAP; } /* access ok? */
Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/exec/cpu-defs.h | 3 +++ include/exec/memattrs.h | 2 -- accel/tcg/cputlb.c | 5 +---- target/sparc/mmu_helper.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-)