From patchwork Wed Apr 12 11:43:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 672619 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:184:0:0:0:0 with SMTP id p4csp288252wrx; Wed, 12 Apr 2023 04:46:55 -0700 (PDT) X-Google-Smtp-Source: AKy350Zu6ts0ELSGiZZhd0D+KI5G+LN3RaVTT1mOcQwA74cIMx9LLi4z92Hg363Mw1VUhNlTLGdk X-Received: by 2002:a05:6214:d81:b0:5ee:e4b2:d95b with SMTP id e1-20020a0562140d8100b005eee4b2d95bmr2889084qve.50.1681300014854; Wed, 12 Apr 2023 04:46:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681300014; cv=none; d=google.com; s=arc-20160816; b=YVPJLFJmr+cchF5dKG4GxlT87D5tIJ2DUboCpYw/jgFMi6RxSTz97lCpmDQoWO97K9 sAj8o/9GBHBNrpzEPLUTwjVcclfD033/BD/9ngdiZTugocZnX5s/WyxGuelAIL3RlSIf bCr+pQp1e4uhcVuFEscB3ztgnJWPxLTJjXR5xadsnR02RzMbGpguunSaYYVRkusjiCWl 3Ki3fjVOxoaMtQybA9q184UzYb2DZyAamdzCVrPMbkw9B16/Xul2NhhGyl4hzIw/Rzhs gQfq5u0w0JKsTjfRJRuoJT7UcCv0FRRFx6nYek87Ph9Riz/nQSbUJeKs83xS3uNGn1ml rnlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EKbGyzdb6cvD2agcBZ2QYZh6VK7dmyekZkQ2foWy+l8=; b=nWzOCJM6+/ml1KX/CWTr0vfpp4D8KfjYAI8IiRPzWAzym0zWTaa5pgLERAyJRKP3qw gUncQk7chbhapxPBEi9jydJCZdbXc7MpgAtP2sxe96TnPxoZ1Qzzs5oWKMY/NFIROEL/ PHSd20CFAbLWKASC6aDnfuN/grClsjt5vN+Y5E7LisjrDs0dWQgFnORBYkS/T0qRGGFz ctG/ZNt1F9sYA/iNIWqbvWQBDaNfWIFI0JZgScHcJOJqMrUEVqJDNNWpBaPtU/RsDTmq Zy9VcFH8cRhWLzBI1lzt/xLo6QiHVkYcoEU/5TTvP7E+gHNsh9p9xeh2AlomXUvDw5L1 X+Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ymQZcciH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 19-20020ac85753000000b003e4e46f881asi10470050qtx.611.2023.04.12.04.46.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Apr 2023 04:46:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ymQZcciH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtC-0004sX-NB; Wed, 12 Apr 2023 07:43:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYt6-0004k3-5p for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:44 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt3-0002Nb-9K for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:43 -0400 Received: by mail-wr1-x432.google.com with SMTP id i3so1256767wrc.4 for ; Wed, 12 Apr 2023 04:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299818; x=1683891818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EKbGyzdb6cvD2agcBZ2QYZh6VK7dmyekZkQ2foWy+l8=; b=ymQZcciH+u37PRMsU3Wcipl5CA7nVULsKwNKHjqCc4JdXQCa5diPsXjgEjpyetRc70 5Ns6tXzLNv5DTk1Z1q16GeDS52HDPYTexFysvWoQc1UH73As2Qzf+aaNzSftlFoudo5p bZNMm8EboEdCQ77qtHH56M9kRexXcdYpLGeUtINOfM0TVgYHvZeqYNQCMoY5G+0fofFj UpJz3gw24eXem84/1sEm+ylQcVpgB2yoPM+kaIpIhffRQxtjRMKUBp5rWJQsvQLW3kUN gpougmr6s7BI1D+HmcJD/X46wRl9uP0PzLxlS5ncMXFCVIIOH8r8fxqdcOUBVDUClHJl qEdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299818; x=1683891818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EKbGyzdb6cvD2agcBZ2QYZh6VK7dmyekZkQ2foWy+l8=; b=zFED0FUyP0AROIA/wPqfQ/pDcWeGJoXHUnQJI+WQkR8EdwJzSMq/OWfCtXLjgBIiTs bouUmBwYe/+C7HtwwQH2KzhsYTga3W7Mngcp1b+2m0t9bDqZknoxsGWwtFmrjXubRWQF uaH5IWuC6rRPX1g9R9xWk6i11rJfbLlF032TjMIdY3h8cRQQ0Bxmp0V7+GjaHNuQalnq yqGlW1P3cnPqIdsa6Cg6CY7sb9bMGCutX6Gf3QDgfQ17eqR2lx6MDC0T4voUnN59Lb6M UBGbOZDTuZYNf6zII4Pg/rGjvGJcDrIq+v/jyFxWYnwdlC/EOMVHPFlI/05fKDJEr70I DkPg== X-Gm-Message-State: AAQBX9fH8eVKu6sl1PLN9qXWRcFnfgVWhEsiLt9ZnFSUtgpritIlSkkv Rb9kvIbErJViBb74YMHzUwkfhk4+PjAiInnvCQ8gXxOF X-Received: by 2002:adf:ef4d:0:b0:2ef:e73d:605d with SMTP id c13-20020adfef4d000000b002efe73d605dmr1629175wrp.30.1681299817778; Wed, 12 Apr 2023 04:43:37 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH v7 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Date: Wed, 12 Apr 2023 13:43:11 +0200 Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: LIU Zhiwei Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com> [rth: Adjust trans_rvf.c.inc as well; use the typedef] Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org> --- target/riscv/cpu.h | 15 ++++++------ target/riscv/cpu_helper.c | 11 +++++---- target/riscv/translate.c | 32 +++++++++++-------------- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 8 +++---- 5 files changed, 32 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ba11279716..51d39687fe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -631,18 +631,17 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) -#define TB_FLAGS_MSTATUS_FS MSTATUS_FS -#define TB_FLAGS_MSTATUS_VS MSTATUS_VS #include "exec/cpu-all.h" FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, LMUL, 3, 3) -FIELD(TB_FLAGS, SEW, 6, 3) -/* Skip MSTATUS_VS (0x600) bits */ -FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) -FIELD(TB_FLAGS, VILL, 12, 1) -/* Skip MSTATUS_FS (0x6000) bits */ +FIELD(TB_FLAGS, FS, 3, 2) +/* Vector flags */ +FIELD(TB_FLAGS, VS, 5, 2) +FIELD(TB_FLAGS, LMUL, 7, 3) +FIELD(TB_FLAGS, SEW, 10, 3) +FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) +FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1d90977d46..8412ef26ee 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -79,16 +79,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #ifdef CONFIG_USER_ONLY - flags |= TB_FLAGS_MSTATUS_FS; - flags |= TB_FLAGS_MSTATUS_VS; + flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); + flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); #else flags |= cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { - flags |= env->mstatus & MSTATUS_FS; + flags = FIELD_DP32(flags, TB_FLAGS, FS, + get_field(env->mstatus, MSTATUS_FS)); } - if (riscv_cpu_vector_enabled(env)) { - flags |= env->mstatus & MSTATUS_VS; + flags = FIELD_DP32(flags, TB_FLAGS, VS, + get_field(env->mstatus, MSTATUS_VS)); } if (riscv_has_ext(env, RVH)) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebd00529ff..411e771e6f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,10 +64,10 @@ typedef struct DisasContext { RISCVMXL xl; uint32_t misa_ext; uint32_t opcode; - uint32_t mstatus_fs; - uint32_t mstatus_vs; - uint32_t mstatus_hs_fs; - uint32_t mstatus_hs_vs; + RISCVExtStatus mstatus_fs; + RISCVExtStatus mstatus_vs; + RISCVExtStatus mstatus_hs_fs; + RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_fs are: - * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx) return; } - if (ctx->mstatus_fs != MSTATUS_FS) { + if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_fs = MSTATUS_FS; + ctx->mstatus_fs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } - if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { + if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs = MSTATUS_FS; + ctx->mstatus_hs_fs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_vs are: - * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx) { TCGv tmp; - if (ctx->mstatus_vs != MSTATUS_VS) { + if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_vs = MSTATUS_VS; + ctx->mstatus_vs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } - if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { + if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs = MSTATUS_VS; + ctx->mstatus_hs_vs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); - ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; - ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; + ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); + ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); ctx->priv_ver = env->priv_ver; ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext = env->misa_ext; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 9e9fa2087a..b2de4fcf3f 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -19,7 +19,7 @@ */ #define REQUIRE_FPU do {\ - if (ctx->mstatus_fs == 0) \ + if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \ if (!ctx->cfg_ptr->ext_zfinx) \ return false; \ } while (0) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ca3c4c1a3d..ecbdf1b3d7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, int8_t asize, static bool require_rvv(DisasContext *s) { - return s->mstatus_vs != 0; + return s->mstatus_vs != EXT_STATUS_DISABLED; } static bool require_rvf(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; } @@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s) static bool require_scale_rvf(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; } @@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s) static bool require_scale_rvfmin(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; }