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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 17/35] crypto: Add aesdec_IMC Date: Fri, 2 Jun 2023 19:34:08 -0700 Message-Id: <20230603023426.1064431-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a primitive for InvMixColumns. Signed-off-by: Richard Henderson --- host/include/generic/host/aes-round.h | 3 ++ include/crypto/aes-round.h | 18 +++++++++ crypto/aes.c | 57 +++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/host/include/generic/host/aes-round.h b/host/include/generic/host/aes-round.h index 7c48db24b6..1e9b97d274 100644 --- a/host/include/generic/host/aes-round.h +++ b/host/include/generic/host/aes-round.h @@ -15,6 +15,9 @@ void aesenc_MC_accel(AESState *, const AESState *, bool) void aesenc_SB_SR_accel(AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); +void aesdec_IMC_accel(AESState *, const AESState *, bool) + QEMU_ERROR("unsupported accel"); + void aesdec_ISB_ISR_accel(AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h index f25e9572a3..2d962ede0b 100644 --- a/include/crypto/aes-round.h +++ b/include/crypto/aes-round.h @@ -74,4 +74,22 @@ static inline void aesdec_ISB_ISR(AESState *r, const AESState *st, bool be) } } +/* + * Perform InvMixColumns. + */ + +void aesdec_IMC_gen(AESState *ret, const AESState *st); +void aesdec_IMC_genrev(AESState *ret, const AESState *st); + +static inline void aesdec_IMC(AESState *r, const AESState *st, bool be) +{ + if (HAVE_AES_ACCEL) { + aesdec_IMC_accel(r, st, be); + } else if (HOST_BIG_ENDIAN == be) { + aesdec_IMC_gen(r, st); + } else { + aesdec_IMC_genrev(r, st); + } +} + #endif /* CRYPTO_AES_ROUND_H */ diff --git a/crypto/aes.c b/crypto/aes.c index c7123eddd5..4e654e5404 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -1402,6 +1402,63 @@ void aesdec_ISB_ISR_genrev(AESState *r, const AESState *st) aesdec_ISB_ISR_swap(r, st, true); } +/* Perform InvMixColumns. */ +static inline void +aesdec_IMC_swap(AESState *r, const AESState *st, bool swap) +{ + int swap_b = swap * 0xf; + int swap_w = swap * 0x3; + bool be = HOST_BIG_ENDIAN ^ swap; + uint32_t t; + + /* Note that AES_imc is encoded for big-endian. */ + t = (AES_imc[st->b[swap_b ^ 0x0]][0] ^ + AES_imc[st->b[swap_b ^ 0x1]][1] ^ + AES_imc[st->b[swap_b ^ 0x2]][2] ^ + AES_imc[st->b[swap_b ^ 0x3]][3]); + if (!be) { + t = bswap32(t); + } + r->w[swap_w ^ 0] = t; + + t = (AES_imc[st->b[swap_b ^ 0x4]][0] ^ + AES_imc[st->b[swap_b ^ 0x5]][1] ^ + AES_imc[st->b[swap_b ^ 0x6]][2] ^ + AES_imc[st->b[swap_b ^ 0x7]][3]); + if (!be) { + t = bswap32(t); + } + r->w[swap_w ^ 1] = t; + + t = (AES_imc[st->b[swap_b ^ 0x8]][0] ^ + AES_imc[st->b[swap_b ^ 0x9]][1] ^ + AES_imc[st->b[swap_b ^ 0xA]][2] ^ + AES_imc[st->b[swap_b ^ 0xB]][3]); + if (!be) { + t = bswap32(t); + } + r->w[swap_w ^ 2] = t; + + t = (AES_imc[st->b[swap_b ^ 0xC]][0] ^ + AES_imc[st->b[swap_b ^ 0xD]][1] ^ + AES_imc[st->b[swap_b ^ 0xE]][2] ^ + AES_imc[st->b[swap_b ^ 0xF]][3]); + if (!be) { + t = bswap32(t); + } + r->w[swap_w ^ 3] = t; +} + +void aesdec_IMC_gen(AESState *r, const AESState *st) +{ + aesdec_IMC_swap(r, st, false); +} + +void aesdec_IMC_genrev(AESState *r, const AESState *st) +{ + aesdec_IMC_swap(r, st, true); +} + /** * Expand the cipher key into the encryption key schedule. */