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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 28/35] crypto: Add aesdec_ISB_ISR_AK_IMC Date: Fri, 2 Jun 2023 19:34:19 -0700 Message-Id: <20230603023426.1064431-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey + InvMixColumns. Signed-off-by: Richard Henderson --- host/include/generic/host/aes-round.h | 4 ++++ include/crypto/aes-round.h | 21 +++++++++++++++++++++ crypto/aes.c | 20 ++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/host/include/generic/host/aes-round.h b/host/include/generic/host/aes-round.h index 848436379d..84f82e53d8 100644 --- a/host/include/generic/host/aes-round.h +++ b/host/include/generic/host/aes-round.h @@ -25,6 +25,10 @@ void aesdec_IMC_accel(AESState *, const AESState *, bool) void aesdec_ISB_ISR_accel(AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); +void aesdec_ISB_ISR_AK_IMC_accel(AESState *, const AESState *, + const AESState *, bool) + QEMU_ERROR("unsupported accel"); + void aesdec_ISB_ISR_IMC_AK_accel(AESState *, const AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h index 352687ce11..b48b87671c 100644 --- a/include/crypto/aes-round.h +++ b/include/crypto/aes-round.h @@ -113,6 +113,27 @@ static inline void aesdec_IMC(AESState *r, const AESState *st, bool be) } } +/* + * Perform InvSubBytes + InvShiftRows + AddRoundKey + InvMixColumns. + */ + +void aesdec_ISB_ISR_AK_IMC_gen(AESState *ret, const AESState *st, + const AESState *rk); +void aesdec_ISB_ISR_AK_IMC_genrev(AESState *ret, const AESState *st, + const AESState *rk); + +static inline void aesdec_ISB_ISR_AK_IMC(AESState *r, const AESState *st, + const AESState *rk, bool be) +{ + if (HAVE_AES_ACCEL) { + aesdec_ISB_ISR_AK_IMC_accel(r, st, rk, be); + } else if (HOST_BIG_ENDIAN == be) { + aesdec_ISB_ISR_AK_IMC_gen(r, st, rk); + } else { + aesdec_ISB_ISR_AK_IMC_genrev(r, st, rk); + } +} + /* * Perform InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. */ diff --git a/crypto/aes.c b/crypto/aes.c index 1696086868..c0e4bc5580 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -1571,6 +1571,26 @@ void aesdec_ISB_ISR_IMC_AK_genrev(AESState *r, const AESState *st, aesdec_ISB_ISR_IMC_AK_swap(r, st, rk, true); } +void aesdec_ISB_ISR_AK_IMC_gen(AESState *r, const AESState *st, + const AESState *rk) +{ + AESState t; + + aesdec_ISB_ISR_gen(&t, st); + t.v ^= rk->v; + aesdec_IMC_gen(r, &t); +} + +void aesdec_ISB_ISR_AK_IMC_genrev(AESState *r, const AESState *st, + const AESState *rk) +{ + AESState t; + + aesdec_ISB_ISR_genrev(&t, st); + t.v ^= rk->v; + aesdec_IMC_genrev(r, &t); +} + /** * Expand the cipher key into the encryption key schedule. */