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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 32/35] crypto: Remove AES_shifts, AES_ishifts Date: Fri, 2 Jun 2023 19:34:23 -0700 Message-Id: <20230603023426.1064431-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::731; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x731.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These arrays are no longer used, replaced by AES_SH_*, AES_ISH_*. Signed-off-by: Richard Henderson --- include/crypto/aes.h | 4 ---- crypto/aes.c | 14 -------------- 2 files changed, 18 deletions(-) diff --git a/include/crypto/aes.h b/include/crypto/aes.h index 24b073d569..aa8b54065d 100644 --- a/include/crypto/aes.h +++ b/include/crypto/aes.h @@ -30,10 +30,6 @@ void AES_decrypt(const unsigned char *in, unsigned char *out, extern const uint8_t AES_sbox[256]; extern const uint8_t AES_isbox[256]; -/* AES ShiftRows and InvShiftRows */ -extern const uint8_t AES_shifts[16]; -extern const uint8_t AES_ishifts[16]; - /* AES MixColumns, for use with rot32. */ extern const uint32_t AES_mc_rot[256]; diff --git a/crypto/aes.c b/crypto/aes.c index c0e4bc5580..4438d4dcdc 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -131,13 +131,6 @@ enum { AES_SH_F = 0xb, }; -const uint8_t AES_shifts[16] = { - AES_SH_0, AES_SH_1, AES_SH_2, AES_SH_3, - AES_SH_4, AES_SH_5, AES_SH_6, AES_SH_7, - AES_SH_8, AES_SH_9, AES_SH_A, AES_SH_B, - AES_SH_C, AES_SH_D, AES_SH_E, AES_SH_F, -}; - /* AES InvShiftRows, for complete unrolling. */ enum { AES_ISH_0 = 0x0, @@ -158,13 +151,6 @@ enum { AES_ISH_F = 0x3, }; -const uint8_t AES_ishifts[16] = { - AES_ISH_0, AES_ISH_1, AES_ISH_2, AES_ISH_3, - AES_ISH_4, AES_ISH_5, AES_ISH_6, AES_ISH_7, - AES_ISH_8, AES_ISH_9, AES_ISH_A, AES_ISH_B, - AES_ISH_C, AES_ISH_D, AES_ISH_E, AES_ISH_F, -}; - /* * MixColumns lookup table, for use with rot32. * From Arm ARM pseudocode.