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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id e91-20020a17090a6fe400b002508d73f4e8sm3914289pjk.57.2023.06.02.19.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 19:34:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH 04/35] crypto: Add aesenc_SB_SR Date: Fri, 2 Jun 2023 19:33:55 -0700 Message-Id: <20230603023426.1064431-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230603023426.1064431-1-richard.henderson@linaro.org> References: <20230603023426.1064431-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Start adding infrastructure for accelerating guest AES. Begin with a SubBytes + ShiftRows primitive. Signed-off-by: Richard Henderson --- host/include/generic/host/aes-round.h | 15 +++++++++ include/crypto/aes-round.h | 41 +++++++++++++++++++++++ crypto/aes.c | 47 +++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 host/include/generic/host/aes-round.h create mode 100644 include/crypto/aes-round.h diff --git a/host/include/generic/host/aes-round.h b/host/include/generic/host/aes-round.h new file mode 100644 index 0000000000..598242c603 --- /dev/null +++ b/host/include/generic/host/aes-round.h @@ -0,0 +1,15 @@ +/* + * No host specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HOST_AES_ROUND_H +#define HOST_AES_ROUND_H + +#define HAVE_AES_ACCEL false +#define ATTR_AES_ACCEL + +void aesenc_SB_SR_accel(AESState *, const AESState *, bool) + QEMU_ERROR("unsupported accel"); + +#endif diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h new file mode 100644 index 0000000000..784e1daee6 --- /dev/null +++ b/include/crypto/aes-round.h @@ -0,0 +1,41 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * AES round fragments, generic version + * + * Copyright (C) 2023 Linaro, Ltd. + */ + +#ifndef CRYPTO_AES_ROUND_H +#define CRYPTO_AES_ROUND_H + +/* Hosts with acceleration will usually need a 16-byte vector type. */ +typedef uint8_t AESStateVec __attribute__((vector_size(16))); + +typedef union { + uint8_t b[16]; + uint32_t w[4]; + uint64_t d[4]; + AESStateVec v; +} AESState; + +#include "host/aes-round.h" + +/* + * Perform SubBytes + ShiftRows. + */ + +void aesenc_SB_SR_gen(AESState *ret, const AESState *st); +void aesenc_SB_SR_genrev(AESState *ret, const AESState *st); + +static inline void aesenc_SB_SR(AESState *r, const AESState *st, bool be) +{ + if (HAVE_AES_ACCEL) { + aesenc_SB_SR_accel(r, st, be); + } else if (HOST_BIG_ENDIAN == be) { + aesenc_SB_SR_gen(r, st); + } else { + aesenc_SB_SR_genrev(r, st); + } +} + +#endif /* CRYPTO_AES_ROUND_H */ diff --git a/crypto/aes.c b/crypto/aes.c index 1309a13e91..708838315a 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -29,6 +29,7 @@ */ #include "qemu/osdep.h" #include "crypto/aes.h" +#include "crypto/aes-round.h" typedef uint32_t u32; typedef uint8_t u8; @@ -1251,6 +1252,52 @@ static const u32 rcon[] = { 0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ }; +/* Perform SubBytes + ShiftRows. */ +static inline void +aesenc_SB_SR_swap(AESState *r, const AESState *st, bool swap) +{ + const int swap_b = swap ? 15 : 0; + uint8_t t; + + /* These four indexes are not swizzled. */ + r->b[swap_b ^ 0x0] = AES_sbox[st->b[swap_b ^ AES_SH_0]]; + r->b[swap_b ^ 0x4] = AES_sbox[st->b[swap_b ^ AES_SH_4]]; + r->b[swap_b ^ 0x8] = AES_sbox[st->b[swap_b ^ AES_SH_8]]; + r->b[swap_b ^ 0xc] = AES_sbox[st->b[swap_b ^ AES_SH_C]]; + + /* Otherwise, break cycles. */ + + t = AES_sbox[st->b[swap_b ^ AES_SH_D]]; + r->b[swap_b ^ 0x1] = AES_sbox[st->b[swap_b ^ AES_SH_1]]; + r->b[swap_b ^ 0x5] = AES_sbox[st->b[swap_b ^ AES_SH_5]]; + r->b[swap_b ^ 0x9] = AES_sbox[st->b[swap_b ^ AES_SH_9]]; + r->b[swap_b ^ 0xd] = t; + + t = AES_sbox[st->b[swap_b ^ AES_SH_A]]; + r->b[swap_b ^ 0x2] = AES_sbox[st->b[swap_b ^ AES_SH_2]]; + r->b[swap_b ^ 0xa] = t; + + t = AES_sbox[st->b[swap_b ^ AES_SH_E]]; + r->b[swap_b ^ 0x6] = AES_sbox[st->b[swap_b ^ AES_SH_6]]; + r->b[swap_b ^ 0xe] = t; + + t = AES_sbox[st->b[swap_b ^ AES_SH_7]]; + r->b[swap_b ^ 0x3] = AES_sbox[st->b[swap_b ^ AES_SH_3]]; + r->b[swap_b ^ 0xf] = AES_sbox[st->b[swap_b ^ AES_SH_F]]; + r->b[swap_b ^ 0xb] = AES_sbox[st->b[swap_b ^ AES_SH_B]]; + r->b[swap_b ^ 0x7] = t; +} + +void aesenc_SB_SR_gen(AESState *r, const AESState *st) +{ + aesenc_SB_SR_swap(r, st, false); +} + +void aesenc_SB_SR_genrev(AESState *r, const AESState *st) +{ + aesenc_SB_SR_swap(r, st, true); +} + /** * Expand the cipher key into the encryption key schedule. */