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([2602:47:d483:7301:a064:e3f9:a812:973b]) by smtp.gmail.com with ESMTPSA id g14-20020a170902868e00b001bc2831e1a9sm13446584plo.90.2023.08.16.11.03.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 11:03:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/18] linux-user/arm: Add vdso Date: Wed, 16 Aug 2023 11:03:32 -0700 Message-Id: <20230816180338.572576-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230816180338.572576-1-richard.henderson@linaro.org> References: <20230816180338.572576-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The thumb vdso will only be used for m-profile, as all of our a-profile cpus support arm mode. Signed-off-by: Richard Henderson --- linux-user/arm/signal.c | 30 +++--- linux-user/elfload.c | 24 +++++ linux-user/arm/Makefile.vdso | 17 +++ linux-user/arm/meson.build | 18 ++++ linux-user/arm/vdso-arm-be.so | Bin 0 -> 2712 bytes linux-user/arm/vdso-arm-le.so | Bin 0 -> 2712 bytes linux-user/arm/vdso-thm-be.so | Bin 0 -> 2684 bytes linux-user/arm/vdso-thm-le.so | Bin 0 -> 2684 bytes linux-user/arm/vdso.S | 193 ++++++++++++++++++++++++++++++++++ linux-user/arm/vdso.ld | 67 ++++++++++++ 10 files changed, 332 insertions(+), 17 deletions(-) create mode 100644 linux-user/arm/Makefile.vdso create mode 100755 linux-user/arm/vdso-arm-be.so create mode 100755 linux-user/arm/vdso-arm-le.so create mode 100755 linux-user/arm/vdso-thm-be.so create mode 100755 linux-user/arm/vdso-thm-le.so create mode 100644 linux-user/arm/vdso.S create mode 100644 linux-user/arm/vdso.ld diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index cf99fd7b8a..bd160b113b 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -167,9 +167,8 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, int usig, abi_ulong handler = 0; abi_ulong handler_fdpic_GOT = 0; abi_ulong retcode; - int thumb, retcode_idx; - int is_fdpic = info_is_fdpic(((TaskState *)thread_cpu->opaque)->info); - bool copy_retcode; + bool thumb; + bool is_fdpic = info_is_fdpic(((TaskState *)thread_cpu->opaque)->info); if (is_fdpic) { /* In FDPIC mode, ka->_sa_handler points to a function @@ -184,9 +183,7 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, int usig, } else { handler = ka->_sa_handler; } - thumb = handler & 1; - retcode_idx = thumb + (ka->sa_flags & TARGET_SA_SIGINFO ? 2 : 0); uint32_t cpsr = cpsr_read(env); @@ -202,24 +199,23 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, int usig, cpsr &= ~CPSR_E; } + /* Our vdso default_sigreturn label is a table of entry points. */ + int idx = is_fdpic * 2 + ((ka->sa_flags & TARGET_SA_SIGINFO) != 0); + retcode = default_sigreturn + idx * 16; + + /* + * Put the sigreturn code on the stack no matter which return + * mechanism we use in order to remain ABI compliant. + */ + memcpy(frame->retcode, g2h_untagged(retcode & ~1), 16); + if (ka->sa_flags & TARGET_SA_RESTORER) { if (is_fdpic) { + /* Place the function descriptor in slot 3. */ __put_user((abi_ulong)ka->sa_restorer, &frame->retcode[3]); - retcode = (sigreturn_fdpic_tramp + - retcode_idx * RETCODE_BYTES + thumb); - copy_retcode = true; } else { retcode = ka->sa_restorer; - copy_retcode = false; } - } else { - retcode = default_sigreturn + retcode_idx * RETCODE_BYTES + thumb; - copy_retcode = true; - } - - /* Copy the code to the stack slot for ABI compatibility. */ - if (copy_retcode) { - memcpy(frame->retcode, g2h_untagged(retcode & ~1), RETCODE_BYTES); } env->regs[0] = usig; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 98cb1ff053..8c2ca3520f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -580,6 +580,30 @@ static const char *get_elf_platform(void) #undef END } +#if TARGET_BIG_ENDIAN +# include "vdso-arm-be.c.inc" +# include "vdso-thm-be.c.inc" +#else +# include "vdso-arm-le.c.inc" +# include "vdso-thm-le.c.inc" +#endif + +static const VdsoImageInfo *vdso_image_info(void) +{ + ARMCPU *cpu = ARM_CPU(thread_cpu); + + /* + * The only cpus we support that do *not* have arm mode are m-profile. + * It's not really possible to run Linux on these, but this config is + * useful for testing gcc. In any case, choose the vdso image that + * will work for the target cpu. + */ + return (arm_feature(&cpu->env, ARM_FEATURE_M) + ? &vdso_thm_image_info + : &vdso_arm_image_info); +} +#define vdso_image_info vdso_image_info + #else /* 64 bit ARM definitions */ #define ELF_START_MMAP 0x80000000 diff --git a/linux-user/arm/Makefile.vdso b/linux-user/arm/Makefile.vdso new file mode 100644 index 0000000000..e031a3d549 --- /dev/null +++ b/linux-user/arm/Makefile.vdso @@ -0,0 +1,17 @@ +CROSS_CC ?= arm-linux-gnueabihf-gcc +LDFLAGS := -nostdlib -shared -Wl,-T,vdso.ld \ + -Wl,-h,linux-vdso.so.1 -Wl,--hash-style=both -Wl,--build-id=sha1 + +all: vdso-arm-le.so vdso-arm-be.so vdso-thm-le.so vdso-thm-be.so + +vdso-arm-le.so: vdso.S vdso.ld Makefile.vdso + $(CROSS_CC) $(LDFLAGS) -mlittle-endian -marm vdso.S -o $@ + +vdso-arm-be.so: vdso.S vdso.ld Makefile.vdso + $(CROSS_CC) $(LDFLAGS) -mbig-endian -marm vdso.S -o $@ + +vdso-thm-le.so: vdso.S vdso.ld Makefile.vdso + $(CROSS_CC) $(LDFLAGS) -mlittle-endian -mthumb vdso.S -o $@ + +vdso-thm-be.so: vdso.S vdso.ld Makefile.vdso + $(CROSS_CC) $(LDFLAGS) -mbig-endian -mthumb vdso.S -o $@ diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 5a93c925cf..66072411d6 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -5,3 +5,21 @@ syscall_nr_generators += { arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ], output: '@BASENAME@_nr.h') } + +# ??? There does not seem to be a way to do +# when: ['TARGET_ARM', !'TARGET_WORDS_BIGENDIAN'] +# so we'd need to add TARGET_WORDS_LITTLEENDIAN. +# In the meantime, build both files for arm and armeb. + +gen = [ + gen_vdso.process('vdso-arm-be.so', + extra_args: ['-s', 'sigreturn_codes', '-p', 'vdso_arm']), + gen_vdso.process('vdso-arm-le.so', + extra_args: ['-s', 'sigreturn_codes', '-p', 'vdso_arm']), + gen_vdso.process('vdso-thm-be.so', + extra_args: ['-s', 'sigreturn_codes', '-p', 'vdso_thm']), + gen_vdso.process('vdso-thm-le.so', + extra_args: ['-s', 'sigreturn_codes', '-p', 'vdso_thm']), +] + +linux_user_ss.add(when: 'TARGET_ARM', if_true: gen) diff --git a/linux-user/arm/vdso-arm-be.so b/linux-user/arm/vdso-arm-be.so new file mode 100755 index 0000000000000000000000000000000000000000..b642b8e5e9322513c289a75ed431645e5f139475 GIT binary patch literal 2712 zcmbtWO-x)>6h3eMX<-;D!8UY(kr-3USSe|mXbb}brDm8m6k@H3kH^fwObRn(=Fx(w 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zA8GCPC~P-24m$2*?j-L3`Ul{}8;svnQ}OK^TV9;lkrlhFEiKov%U zbJ1(c`B5eT#^$)-ZyHb~+Rp{keyjsTy`B{MwBJ$Rk9)#=Ck~;lMb&7KMF1hzx~lNw zo@>#e^*gowD*SlIv3~G(2dLUNRxG^+Xvz{M@F5$%=y;9bLBD-ikk_;mwD$WOF-L=H literal 0 HcmV?d00001 diff --git a/linux-user/arm/vdso.S b/linux-user/arm/vdso.S new file mode 100644 index 0000000000..57e405d453 --- /dev/null +++ b/linux-user/arm/vdso.S @@ -0,0 +1,193 @@ +/* + * arm linux replacement vdso. + * + * Copyright 2023 Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + + .text + .eabi_attribute Tag_FP_arch, 0 + +#ifdef __thumb__ + .thumb + .arch armv7-m + .eabi_attribute Tag_ARM_ISA_use, 0 + .eabi_attribute Tag_CPU_arch, 13 /* TAG_CPU_ARCH_V7_M */ + +.macro raw_syscall n + .ifne \n < 0x100 + mov r7, #\n + .else + ldr r7, =\n + .endif + swi #0 +.endm + +.macro fdpic_thunk ofs + ldr r3, [sp, #\ofs] + ldmia r2, {r2, r3} + mov r9, r3 + bx r2 +.endm + +#else + .arm + .arch armv4t + .eabi_attribute Tag_THUMB_ISA_use, 0 + +.macro raw_syscall n + .ifne \n < 0x100 + mov r7, #\n + .else + mov r7, #(\n & 0xff) + orr r7, r7, #(\n & 0xff00) + .endif + svc #(\n | __NR_OABI_SYSCALL_BASE) +.endm + +.macro fdpic_thunk ofs + ldr r3, [sp, #\ofs] + ldmia r3, {r3, r9} + bx r3 +.endm + +#endif + +.macro endf name + .globl \name + .type \name, %function + .size \name, . - \name +.endm + +/* + * We must save/restore r7 for the EABI syscall number. + * While we're doing that, we might as well save LR to get a free return, + * and a branch that is interworking back to ARMv5. + */ + +.macro SYSCALL name, nr +\name: + .cfi_startproc + push {r7, lr} + .cfi_adjust_cfa_offset 8 + .cfi_offset r7, -8 + .cfi_offset lr, -4 + raw_syscall \nr + pop {r7, pc} + .cfi_endproc +endf \name +.endm + +SYSCALL __vdso_clock_gettime, __NR_clock_gettime +SYSCALL __vdso_clock_gettime64, __NR_clock_gettime64 +SYSCALL __vdso_clock_getres, __NR_clock_getres +SYSCALL __vdso_gettimeofday, __NR_gettimeofday + + +/* + * We, like the real kernel, use a table of sigreturn trampolines. + * Unlike the real kernel, we do not attempt to pack this into as + * few bytes as possible -- simply use 16 bytes per slot. + * + * Within each slot, use the exact same code sequence as the kernel, + * lest we trip up someone doing code inspection. + */ + +/* offsetof(struct sigframe, retcode[3]) */ +#define SIGFRAME_RC3_OFFSET 756 +#define RT_SIGFRAME_RC3_OFFSET 884 + +.macro slot n + .balign 16 + .org sigreturn_codes + 16 * \n +.endm + +/* + * Start the unwind info at least one instruction before the signal + * trampoline, because the unwinder will assume we are returning + * after a call site. + */ + .cfi_startproc simple + .cfi_signal_frame + .cfi_return_column 15 + + .cfi_def_cfa sp, 32 + 64 + .cfi_offset r0, -16 * 4 + .cfi_offset r1, -15 * 4 + .cfi_offset r2, -14 * 4 + .cfi_offset r3, -13 * 4 + .cfi_offset r4, -12 * 4 + .cfi_offset r5, -11 * 4 + .cfi_offset r6, -10 * 4 + .cfi_offset r7, -9 * 4 + .cfi_offset r8, -8 * 4 + .cfi_offset r9, -7 * 4 + .cfi_offset r10, -6 * 4 + .cfi_offset r11, -5 * 4 + .cfi_offset r12, -4 * 4 + .cfi_offset r13, -3 * 4 + .cfi_offset r14, -2 * 4 + .cfi_offset r15, -1 * 4 + + nop + + .balign 16 +sigreturn_codes: + /* [EO]ABI sigreturn */ + slot 0 + raw_syscall __NR_sigreturn + + .cfi_def_cfa_offset 160 + 64 + + /* [EO]ABI rt_sigreturn */ + slot 1 + raw_syscall __NR_rt_sigreturn + + .cfi_endproc + + .macro cfi_fdpic_pc ofs + /* + * fd = *(r13 + ofs) + * pc = *fd + * + * DW_CFA_expression lr (14), length (5), + * DW_OP_breg13, ofs, DW_OP_deref, DW_OP_deref + */ + .cfi_escape 0x10, 14, 5, 0x7d, (\ofs & 0x7f) + 0x80, (\ofs >> 7), 0x06, 0x06 + .endm + + .macro cfi_fdpic_r9 ofs + /* + * fd = *(r13 + ofs) + * r9 = *(fd + 4) + * + * DW_CFA_expression r9, length (7), + * DW_OP_breg13, ofs, DW_OP_deref, + * DW_OP_plus_uconst, 4, DW_OP_deref + */ + .cfi_escape 0x10, 9, 7, 0x7d, (\ofs & 0x7f) + 0x80, (\ofs >> 7), 0x06, 0x23, 4, 0x06 + .endm + + /* FDPIC sigreturn */ + .cfi_startproc + cfi_fdpic_pc SIGFRAME_RC3_OFFSET + cfi_fdpic_r9 SIGFRAME_RC3_OFFSET + + slot 2 + fdpic_thunk SIGFRAME_RC3_OFFSET + .cfi_endproc + + /* FDPIC rt_sigreturn */ + .cfi_startproc + cfi_fdpic_pc RT_SIGFRAME_RC3_OFFSET + cfi_fdpic_r9 RT_SIGFRAME_RC3_OFFSET + + slot 3 + fdpic_thunk RT_SIGFRAME_RC3_OFFSET + .cfi_endproc + + .balign 16 +endf sigreturn_codes diff --git a/linux-user/arm/vdso.ld b/linux-user/arm/vdso.ld new file mode 100644 index 0000000000..3b00adf27a --- /dev/null +++ b/linux-user/arm/vdso.ld @@ -0,0 +1,67 @@ +/* + * Linker script for linux arm replacement vdso. + * + * Copyright 2023 Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +VERSION { + LINUX_2.6 { + global: + __vdso_clock_gettime; + __vdso_gettimeofday; + __vdso_clock_getres; + __vdso_clock_gettime64; + + local: *; + }; +} + + +PHDRS { + phdr PT_PHDR FLAGS(4) PHDRS; + load PT_LOAD FLAGS(7) FILEHDR PHDRS; /* FLAGS=RWX */ + dynamic PT_DYNAMIC FLAGS(4); + eh_frame_hdr PT_GNU_EH_FRAME; + note PT_NOTE FLAGS(4); +} + +SECTIONS { + . = SIZEOF_HEADERS; + + /* + * The following, including the FILEHDRS and PHDRS, are modified + * when we relocate the binary. We want them to be initially + * writable for the relocation; we'll force them read-only after. + */ + .note : { *(.note*) } :load :note + .dynamic : { *(.dynamic) } :load :dynamic + .dynsym : { *(.dynsym) } :load + /* + * There ought not be any real read-write data. + * But since we manipulated the segment layout, + * we have to put these sections somewhere. + */ + .data : { + *(.data*) + *(.sdata*) + *(.got.plt) *(.got) + *(.gnu.linkonce.d.*) + *(.bss*) + *(.dynbss*) + *(.gnu.linkonce.b.*) + } + + .rodata : { *(.rodata*) } + .hash : { *(.hash) } + .gnu.hash : { *(.gnu.hash) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .eh_frame_hdr : { *(.eh_frame_hdr) } :load :eh_frame_hdr + .eh_frame : { *(.eh_frame) } :load + + .text : { *(.text*) } :load +}