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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id fi10-20020a170906da0a00b009ad8796a6aesm8106883ejb.56.2023.10.10.02.31.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types Date: Tue, 10 Oct 2023 11:28:59 +0200 Message-ID: <20231010092901.99189-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending on the mips(32)/mips64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types, both inheriting a common TYPE_MIPS_CPU base type. Keep the current CPU types registered in mips_register_cpudef_type() as 32 or 64-bit, but instead of depending on the binary built being targeting 32/64-bit, check whether the CPU is 64-bit by looking at the CPU_MIPS64 bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-qom.h | 13 ++++++------- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 11 ++++++++++- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 9c98ca1956..1a71509b5e 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MIPS CPU + * QEMU MIPS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -23,13 +23,12 @@ #include "hw/core/cpu.h" #include "qom/object.h" -#ifdef TARGET_MIPS64 -#define TYPE_MIPS_CPU "mips64-cpu" -#else -#define TYPE_MIPS_CPU "mips-cpu" -#endif +#define TYPE_MIPS_CPU "mips-cpu" +#define TYPE_MIPS32_CPU "mips32-cpu" +#define TYPE_MIPS64_CPU "mips64-cpu" -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6b026e6bcf..3b6d0a7a8a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -10,6 +10,9 @@ #include "hw/clock.h" #include "mips-defs.h" +/* Abstract QOM MIPS CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) + #define TCG_GUEST_DEFAULT_MO (0) typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 83ee54f766..f43300dd5e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -605,6 +605,14 @@ static const TypeInfo mips_cpu_types[] = { .abstract = true, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, + }, { + .name = TYPE_MIPS32_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, + }, { + .name = TYPE_MIPS64_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, } }; @@ -621,7 +629,8 @@ static void mips_register_cpudef_type(const struct mips_def_t *def) char *typename = mips_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_MIPS_CPU, + .parent = def->insn_flags & CPU_MIPS64 + ? TYPE_MIPS64_CPU : TYPE_MIPS32_CPU, .class_init = mips_cpu_cpudef_class_init, .class_data = (void *)def, };