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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id a6-20020a170906190600b009ad89697c86sm11081226eje.144.2023.10.12.05.19.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/8] hw/pci-host/designware: Keep host reference in DesignwarePCIEViewport Date: Thu, 12 Oct 2023 14:18:53 +0200 Message-ID: <20231012121857.31873-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PCI root function is irrelevant for the ViewPort; only a reference to the host bridge is required. Since we can directly access the PCI bus, remove the pci_get_bus() call. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/designware.h | 2 +- hw/pci-host/designware.c | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index 9e2caa04e9..e1952ad324 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -32,7 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST) OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT) typedef struct DesignwarePCIEViewport { - DesignwarePCIERoot *root; + DesignwarePCIEHost *host; MemoryRegion cfg; MemoryRegion mem; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index fb46493a05..d12a36b628 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -211,12 +211,11 @@ static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr, uint64_t *val, unsigned len) { DesignwarePCIEViewport *viewport = opaque; - DesignwarePCIERoot *root = viewport->root; + PCIHostState *pci = PCI_HOST_BRIDGE(viewport->host); const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); - PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); - PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn); + PCIDevice *pcidev = pci_find_device(pci->bus, busnum, devfn); if (pcidev) { addr &= pci_config_size(pcidev) - 1; @@ -445,7 +444,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) g_free(name); viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; - viewport->root = root; + viewport->host = host; viewport->inbound = false; viewport->base = 0x0000000000000000ULL; viewport->target = 0x0000000000000000ULL;