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[209.51.188.17]) by mx.google.com with ESMTPS id dc11-20020a056214174b00b0066d09b6c11bsi1215682qvb.526.2023.10.13.07.05.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2023 07:05:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zrAkMmQ9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrImL-0003hP-P1; Fri, 13 Oct 2023 10:04:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrIky-0008Bq-9o for qemu-devel@nongnu.org; Fri, 13 Oct 2023 10:03:13 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrIkv-0002Ry-3T for qemu-devel@nongnu.org; Fri, 13 Oct 2023 10:03:12 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9bda758748eso76301966b.2 for ; Fri, 13 Oct 2023 07:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697205785; x=1697810585; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0NHkF48NQwYUtwEuXHiOGrGxMidZGr1dxHAYpW0iraY=; b=zrAkMmQ9YRQuQ+8mzJf63kEUdBSWPU6K8gr5om45UY0XoPwFeViWSsLu8tD8v6hsEw OS6xUf3DbW++WZWEA3qHqeqLSZbALsgQwL+Ne8ucrCoM0t4k0E3K6Xo9Y4VZ70RJFThc NLnXjVQZkeS2XBsc73oGHVgpcfrYZyohXtWcVt6q2ey2OTnaUVAEahTnDFgDm1vCGwb7 dyngPSPVOjTEf8BgVN24tlr1RMFKxGtWQ/Dfci/r4TIKTn44oBZsAlZuuWaPBCpi7iBb 0uYti9KLlQ8tIwTN7ydYs9r+sv40c+OSKzklUABSDPotbSFBSQjZnICMwI1ynYwo/RXn vzNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697205785; x=1697810585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0NHkF48NQwYUtwEuXHiOGrGxMidZGr1dxHAYpW0iraY=; b=V8hzwCSBuem+IDnPSNVKlsTS1nL5GIvxlXDubNOAbgplogUC9HoaFidC8J0YN41MJ6 Fn6/dgNqo6yMetNixdJ9I+bA2o4WolCo2ik+rYhW74f+njjGI6C65SjrTx9Sb+3NEUS6 ggmqArpWbAqBopYoonApfYFTztq2fiRUQAtXnlbYVqgxZgNEZ7gRSKtqk+QzFWDa1WGb PiiH6Gks3dfbQUnlsDTWy4/G5t8HA0XRWOjG1HrLXI/0c/XV4eOGcUviiQKIQwamCSxk YfP1UehioyV3njrjzGV/kZqUd3VuNgAtHxEiZQ3VgMB7xOKf0nlN6VzMAp+UtqG/f6L7 DwtA== X-Gm-Message-State: AOJu0YxVeCt+uxHZV/NMyQ2+2bqzn7ydP7Ceog2b+1qQfmEGz4RNsdXt aQf+yBCcF/UN7iZ7MimEs1p7tRGxactZki64AZU= X-Received: by 2002:a17:907:2cd9:b0:9ba:1f02:77f2 with SMTP id hg25-20020a1709072cd900b009ba1f0277f2mr11695399ejc.56.1697205785417; Fri, 13 Oct 2023 07:03:05 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id x20-20020a170906299400b009b2f2451381sm12507640eje.182.2023.10.13.07.03.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 07:03:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Xiaojuan Yang , "Michael S. Tsirkin" , qemu-ppc@nongnu.org, Aleksandar Rikalo , David Hildenbrand , qemu-s390x@nongnu.org, "Edgar E. Iglesias" , Jiaxun Yang , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Stafford Horne , Alistair Francis , Yanan Wang , Max Filippov , Artyom Tarasenko , Marcel Apfelbaum , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Laurent Vivier , Aurelien Jarno , qemu-riscv@nongnu.org, Palmer Dabbelt , Yoshinori Sato , Bastian Koppelmann , Bin Meng , Daniel Henrique Barboza , Mark Cave-Ayland , Weiwei Li , Daniel Henrique Barboza , Nicholas Piggin , qemu-arm@nongnu.org, Liu Zhiwei , Marek Vasut , Laurent Vivier , Peter Maydell , Brian Cain , Thomas Huth , Chris Wulff , Sergio Lopez , Richard Henderson , Ilya Leoshkevich , Michael Rolnik Subject: [PATCH v2 11/16] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h' Date: Fri, 13 Oct 2023 16:01:10 +0200 Message-ID: <20231013140116.255-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013140116.255-1-philmd@linaro.org> References: <20231013140116.255-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by moving TYPE_RISCV_CPU_BASE to "target/riscv/cpu.h". "target/riscv/cpu-qom.h" is now fully target agnostic. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu-qom.h | 8 +------- target/riscv/cpu.h | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b78169093f..76efb614a6 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU RISC-V CPU QOM header + * QEMU RISC-V CPU QOM header (target agnostic) * * Copyright (c) 2023 Ventana Micro Systems Inc. * @@ -44,12 +44,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - typedef struct CPUArchState CPURISCVState; OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 144cc94cce..d832696418 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,6 +34,12 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define TCG_GUEST_DEFAULT_MO 0 /*