From patchwork Fri Oct 13 21:28:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733331 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680365wrv; Fri, 13 Oct 2023 14:38:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHU2B+xaXd+9CyLrVWcgi0MOWEUOluPkqBwHdRuZ254DVZQR30NDZAdnzo9YNEq+aOFsAM X-Received: by 2002:a05:6808:cd:b0:3a8:7c67:7cd with SMTP id t13-20020a05680800cd00b003a87c6707cdmr29165817oic.24.1697233114065; Fri, 13 Oct 2023 14:38:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233114; cv=none; d=google.com; s=arc-20160816; b=hNH2WI9rxdpjuvn8RUvmSwFynH5nNPDodURM1u+LtVQTTQCgwd88fAqkqmM9y7pJI5 RyTTbw8pvYiLKgDrHKlUqXddvXHHaWMekXqwdxT1yvo3nQgjUAXcxQrsRSimzmW7T//C TNkY5ACWIyWcYhzXkcY8kX3hOhXGYYxyRJg9iNpAUsztpXih90Ai3uaWArgysrq6Vc18 QfemTLO+en03Bn7BIQY3fpPwhVXAN25C89deQ1LiBJN14fn3gzgZSJvYXFLfjkUNJZvm NqCDgwi5YAAExcHxqN1okVre7R8hhSM1PZN303PZxlV7Pc0lB7xTAp1e59PKgyP+6ld6 MVhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=grK4KzjtSaN3X+3hGAiElB+EhMzZc+yFihTRMQ33SLo=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=FJ0jHfDSB6gpUdB/WNvsmUVkje/r5gdw4uallbX6XTCcPPukOYBdrNs0nlKQYBug2Y uQyM1svs2P6aac/ewLg7fxWJJN8iss17Xg7WRUk9JnEBl8H5xDqm1hh5z6nlsbcL7ySZ tLuah2zuEofPlauZV0OMr4xZSUTsjPcHiY6MXj5HLO1TFdJVzMxsS1dgX+o7YhROwsnF rk3bffHvrLN5MEyQjEw0o6V7bkgSNQVz92kjByvEaXn1joZcUcjjZrS5g3jprTo3tAWL F+je9/RTPItak3cLLRALDNQITA5yfXt2LTkWXM9NF7kdU2jfE+0kZ3QBoUpzoA96W7xk clmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FY8KsrtP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x14-20020a05622a000e00b00417b768db1csi1884424qtw.609.2023.10.13.14.38.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2023 14:38:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FY8KsrtP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrPmA-0001n8-Ql; Fri, 13 Oct 2023 17:32:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrPm5-00013N-Cm for qemu-devel@nongnu.org; Fri, 13 Oct 2023 17:32:49 -0400 Received: from mail-io1-xd2b.google.com ([2607:f8b0:4864:20::d2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrPm2-0001Wa-M9 for qemu-devel@nongnu.org; Fri, 13 Oct 2023 17:32:49 -0400 Received: by mail-io1-xd2b.google.com with SMTP id ca18e2360f4ac-79fa891b645so94620939f.0 for ; Fri, 13 Oct 2023 14:32:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697232765; x=1697837565; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=grK4KzjtSaN3X+3hGAiElB+EhMzZc+yFihTRMQ33SLo=; b=FY8KsrtPdD31KRedNQ6Z0NCVy2WnDWV4BOYWdz8/JmyfovVbFlssIAQ6sjDcJgYaNe 4Sfm/bTW8zTstJ3dmS/Kuzk0hh3rGhDvzYfD0p4n5AV1NiSFe4omDfdNZzBouo8QrUvf 0HcPh9Qxqk+cxXv+7CJYZ41VabU8UyJW96Fk27l9xIs0IK2WSmWI35hp0NP8VvM1ZUzy JOSxEo9QZgRRGXpsNCTTrr71Fo+o5Alcn7Gfg4vs4UOCAHods7cQdk/jyjGZSUR9+r0A LCBq9/4RAUD31zeR8R5QcecEsVjJr8onb/jdzlLKCBdTUjbKP8DVZA9eF4xfv8sO90uy 2JnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697232765; x=1697837565; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=grK4KzjtSaN3X+3hGAiElB+EhMzZc+yFihTRMQ33SLo=; b=C595vZE0h7ET7mBV4rl4rHrZc3JgHBmm2bJCkH+Imjil1o/AqUGomvPVJT9x9mpZkY lYKPV3BehwVYV1dLQIGFghYvND+qMrjM7isrR46dO2SRzcpvsReZbf23uWfkin/Vj/Mk 1vpPkMROtVmyS3BkYK0kD0A5hzSAFCDZ3QoXULn/sxaZpwGyuS2UWfGmyHdii3UGEa55 R3Xp/FGFzom3x4Z2qpVSHYrGEYqLKH5VT2Rz55GNluUawvHCp3ANDEmCImHhOAgpYfGQ 0pCIBW9rBbQNDhVYqcslo30fu31oycbfuA7yP7a/NIpeE+wqfWgRpKYxpPEoiMq0b01l yaJQ== X-Gm-Message-State: AOJu0Yxm2itbPXQZniGNcv4aLPT6pystSJIYVNuMWJ6h9KjwYFX4spEj rNKL1tM9dvN+bWz7n/f8hSAlGr2ShC+Py19b2jo= X-Received: by 2002:a05:6602:2191:b0:795:8805:1378 with SMTP id b17-20020a056602219100b0079588051378mr33404073iob.9.1697232765469; Fri, 13 Oct 2023 14:32:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD insns to decodetree Date: Fri, 13 Oct 2023 14:28:23 -0700 Message-Id: <20231013212846.165724-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16, FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d, FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d, FPSUB16d, FPSUB32d, FXNORd, FXORd. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 26 ++++++ target/sparc/translate.c | 178 +++++++++++++++----------------------- 2 files changed, 98 insertions(+), 106 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 96ba61865a..576349a719 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -264,6 +264,17 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r + FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r + FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r + FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r + FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r + FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r + FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + + FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r + FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d @@ -273,19 +284,34 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s + FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r + FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r + FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + + FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r + FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FANDNOT2d FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s + FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # ... 1d FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s + FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r + FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r + FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r + FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r + FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FORNOT2d FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s + FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # ... 1d FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s + FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 30329b94dd..8b16772a71 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -59,6 +59,15 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() +#define gen_helper_fmul8x16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8x16au ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8x16al ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8sux16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8ulx16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmuld8sux16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmuld8ulx16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1527,20 +1536,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, } #ifdef TARGET_SPARC64 -static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4852,6 +4847,46 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) +static bool do_ddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16) +TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au) +TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al) +TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) +TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) +TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) +TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16) +TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) +TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand) + +TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) +TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) +TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) +TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) +TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) +TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) +TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) +TRANS(FNANDd, VIS1, do_ddd, a, tcg_gen_nand_i64) +TRANS(FANDd, VIS1, do_ddd, a, tcg_gen_and_i64) +TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) +TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) +TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5238,6 +5273,29 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x077: /* VIS I fornot2s */ case 0x07b: /* VIS I fornot1s */ case 0x07d: /* VIS I fors */ + case 0x050: /* VIS I fpadd16 */ + case 0x052: /* VIS I fpadd32 */ + case 0x054: /* VIS I fpsub16 */ + case 0x056: /* VIS I fpsub32 */ + case 0x062: /* VIS I fnor */ + case 0x064: /* VIS I fandnot2 */ + case 0x068: /* VIS I fandnot1 */ + case 0x06c: /* VIS I fxor */ + case 0x06e: /* VIS I fnand */ + case 0x070: /* VIS I fand */ + case 0x072: /* VIS I fxnor */ + case 0x076: /* VIS I fornot2 */ + case 0x07a: /* VIS I fornot1 */ + case 0x07c: /* VIS I for */ + case 0x031: /* VIS I fmul8x16 */ + case 0x033: /* VIS I fmul8x16au */ + case 0x035: /* VIS I fmul8x16al */ + case 0x036: /* VIS I fmul8sux16 */ + case 0x037: /* VIS I fmul8ulx16 */ + case 0x038: /* VIS I fmuld8sux16 */ + case 0x039: /* VIS I fmuld8ulx16 */ + case 0x04b: /* VIS I fpmerge */ + case 0x04d: /* VIS I fexpand */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5295,34 +5353,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x031: /* VIS I fmul8x16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); - break; - case 0x033: /* VIS I fmul8x16au */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au); - break; - case 0x035: /* VIS I fmul8x16al */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al); - break; - case 0x036: /* VIS I fmul8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16); - break; - case 0x037: /* VIS I fmul8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16); - break; - case 0x038: /* VIS I fmuld8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); - break; - case 0x039: /* VIS I fmuld8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); - break; case 0x03a: /* VIS I fpack32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); @@ -5349,34 +5379,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; - case 0x04b: /* VIS I fpmerge */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); - break; case 0x04c: /* VIS II bshuffle */ CHECK_FPU_FEATURE(dc, VIS2); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); break; - case 0x04d: /* VIS I fexpand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); - break; - case 0x050: /* VIS I fpadd16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64); - break; - case 0x052: /* VIS I fpadd32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); - break; - case 0x054: /* VIS I fpsub16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64); - break; - case 0x056: /* VIS I fpsub32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); @@ -5389,46 +5395,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) tcg_gen_movi_i32(cpu_dst_32, 0); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x062: /* VIS I fnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); - break; - case 0x064: /* VIS I fandnot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); - break; - case 0x068: /* VIS I fandnot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); - break; - case 0x06c: /* VIS I fxor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); - break; - case 0x06e: /* VIS I fnand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); - break; - case 0x070: /* VIS I fand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); - break; - case 0x072: /* VIS I fxnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); - break; - case 0x076: /* VIS I fornot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); - break; - case 0x07a: /* VIS I fornot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); - break; - case 0x07c: /* VIS I for */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); - break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd);