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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 63/85] target/sparc: Move PDIST to decodetree Date: Fri, 13 Oct 2023 14:28:24 -0700 Message-Id: <20231013212846.165724-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 576349a719..12db108a31 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -271,6 +271,7 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8b16772a71..5da3170978 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -68,6 +68,7 @@ #define gen_helper_fmuld8ulx16 ({ g_assert_not_reached(); NULL; }) #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) +#define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1549,21 +1550,6 @@ static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } - -static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src0, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - src0 = gen_load_fpr_D(dc, rd); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, src0, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} #endif static void gen_fop_QQ(DisasContext *dc, int rd, int rs, @@ -4887,6 +4873,26 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) +static bool do_dddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src0, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src0 = gen_load_fpr_D(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src0, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5296,6 +5302,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x039: /* VIS I fmuld8ulx16 */ case 0x04b: /* VIS I fpmerge */ case 0x04d: /* VIS I fexpand */ + case 0x03e: /* VIS I pdist */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5371,10 +5378,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x03e: /* VIS I pdist */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); - break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);