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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 08/85] target/sparc: Move BPr to decodetree Date: Fri, 13 Oct 2023 14:27:29 -0700 Message-Id: <20231013212846.165724-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d35; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 70 ++++++++++++++++----------------------- 2 files changed, 32 insertions(+), 41 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 15cd975f4e..838f4cdb1d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -7,4 +7,7 @@ BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 +%d16 20:s2 0:14 +BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 125015fe1e..f72e6eb756 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1292,14 +1292,13 @@ static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) } } -#ifdef TARGET_SPARC64 // Inverted logic -static const int gen_tcg_cond_reg[8] = { - -1, +static const TCGCond gen_tcg_cond_reg[8] = { + TCG_COND_NEVER, /* reserved */ TCG_COND_NE, TCG_COND_GT, TCG_COND_GE, - -1, + TCG_COND_NEVER, /* reserved */ TCG_COND_EQ, TCG_COND_LE, TCG_COND_LT, @@ -1313,16 +1312,6 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) cmp->c2 = tcg_constant_tl(0); } -static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) -{ - DisasCompare cmp; - gen_compare_reg(&cmp, cond, r_src); - - /* The interface is to return a boolean in r_dst. */ - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); -} -#endif - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) { unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); @@ -1362,24 +1351,6 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) } #ifdef TARGET_SPARC64 -static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, - TCGv r_reg) -{ - unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); - target_ulong target = dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &= 0xffffffffULL; - } - flush_cond(dc); - gen_cond_reg(cpu_cond, cond, r_reg); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } -} - static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { @@ -3022,6 +2993,31 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) TRANS(BPcc, 64, do_bpcc, a) TRANS(Bicc, ALL, do_bpcc, a) +static bool trans_BPr(DisasContext *dc, arg_BPr *a) +{ + target_long target; + DisasCompare cmp; + + if (!avail_64(dc)) { + return false; + } + if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) { + return false; + } + + target = dc->pc + a->i * 4; + if (unlikely(AM_CHECK(dc))) { + target &= 0xffffffffULL; + } + + flush_cond(dc); + + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + + return advance_jump_cond(dc, a->a, target); +} + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target = dc->pc + a->i * 4; @@ -3065,15 +3061,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x1: /* V9 BPcc */ g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ - { - target = GET_FIELD_SP(insn, 0, 13) | - (GET_FIELD_SP(insn, 20, 21) << 14); - target = sign_extend(target, 16); - target <<= 2; - cpu_src1 = get_src1(dc, insn); - do_branch_reg(dc, target, insn, cpu_src1); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x5: /* V9 FBPcc */ { int cc = GET_FIELD_SP(insn, 20, 21);