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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id m10-20020a056a00080a00b00690ca4356f1sm579280pfk.198.2023.10.16.23.16.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:16:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 62/90] target/sparc: Move BMASK to decodetree Date: Mon, 16 Oct 2023 23:12:16 -0700 Message-Id: <20231017061244.681584-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017061244.681584-1-richard.henderson@linaro.org> References: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 +++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8bd57f620a..6f136e0602 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -248,6 +248,8 @@ RETRY 10 00001 111110 00000 0 0000000000000 ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r + + BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dab3e83c27..64f1999cba 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4352,6 +4352,18 @@ static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2) TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr) TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl) +static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + tcg_gen_add_tl(dst, s1, s2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, dst, 32, 32); +#else + g_assert_not_reached(); +#endif +} + +TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -4889,7 +4901,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1 __attribute__((unused)); - TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32; TCGv_i64 cpu_src1_64, cpu_src2_64; TCGv_i32 cpu_dst_32 __attribute__((unused)); @@ -5254,15 +5265,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x014: /* VIS I array32 */ case 0x018: /* VIS I alignaddr */ case 0x01a: /* VIS I alignaddrl */ - g_assert_not_reached(); /* in decodetree */ case 0x019: /* VIS II bmask */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs1);