@@ -3,4 +3,8 @@
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
+&bcc i a cond cc
+BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
+Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
+
CALL 01 i:s30
@@ -1367,44 +1367,6 @@ static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
}
#endif
-static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
-{
- unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
- target_ulong target = dc->pc + offset;
-
- if (unlikely(AM_CHECK(dc))) {
- target &= 0xffffffffULL;
- }
- if (cond == 0x0) {
- /* unconditional not taken */
- if (a) {
- dc->pc = dc->npc + 4;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = dc->pc + 4;
- }
- } else if (cond == 0x8) {
- /* unconditional taken */
- if (a) {
- dc->pc = target;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = target;
- tcg_gen_mov_tl(cpu_pc, cpu_npc);
- }
- } else {
- flush_cond(dc);
- gen_cond(cpu_cond, cc, cond, dc);
- if (a) {
- gen_branch_a(dc, target);
- } else {
- gen_branch_n(dc, target);
- }
- }
-}
-
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
{
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
@@ -3046,6 +3008,61 @@ static bool advance_pc(DisasContext *dc)
return true;
}
+static bool advance_jump_uncond_never(DisasContext *dc, bool annul)
+{
+ if (annul) {
+ dc->pc = dc->npc + 4;
+ dc->npc = dc->pc + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dc->pc + 4;
+ }
+ return true;
+}
+
+static bool advance_jump_uncond_always(DisasContext *dc, bool annul,
+ target_ulong dest)
+{
+ if (annul) {
+ dc->pc = dest;
+ dc->npc = dest + 4;
+ } else {
+ dc->pc = dc->npc;
+ dc->npc = dest;
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
+ }
+ return true;
+}
+
+static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest)
+{
+ if (annul) {
+ gen_branch_a(dc, dest);
+ } else {
+ gen_branch_n(dc, dest);
+ }
+ return true;
+}
+
+static bool do_bpcc(DisasContext *dc, arg_bcc *a)
+{
+ target_long target = address_mask_i(dc, dc->pc + a->i * 4);
+
+ switch (a->cond) {
+ case 0x0:
+ return advance_jump_uncond_never(dc, a->a);
+ case 0x8:
+ return advance_jump_uncond_always(dc, a->a, target);
+ default:
+ flush_cond(dc);
+ gen_cond(cpu_cond, a->cc, a->cond, dc);
+ return advance_jump_cond(dc, a->a, target);
+ }
+}
+
+TRANS(Bicc, ALL, do_bpcc, a)
+TRANS(BPcc, 64, do_bpcc, a)
+
static bool trans_CALL(DisasContext *dc, arg_CALL *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
@@ -3083,21 +3100,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
switch (xop) {
#ifdef TARGET_SPARC64
case 0x1: /* V9 BPcc */
- {
- int cc;
-
- target = GET_FIELD_SP(insn, 0, 18);
- target = sign_extend(target, 19);
- target <<= 2;
- cc = GET_FIELD_SP(insn, 20, 21);
- if (cc == 0)
- do_branch(dc, target, insn, 0);
- else if (cc == 2)
- do_branch(dc, target, insn, 1);
- else
- goto illegal_insn;
- goto jmp_insn;
- }
+ g_assert_not_reached(); /* in decodetree */
case 0x3: /* V9 BPr */
{
target = GET_FIELD_SP(insn, 0, 13) |
@@ -3127,13 +3130,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
}
#endif
case 0x2: /* BN+x */
- {
- target = GET_FIELD(insn, 10, 31);
- target = sign_extend(target, 22);
- target <<= 2;
- do_branch(dc, target, insn, 0);
- goto jmp_insn;
- }
+ g_assert_not_reached(); /* in decodetree */
case 0x6: /* FBN+x */
{
if (gen_trap_ifnofpu(dc)) {
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 117 +++++++++++++++++++------------------- 2 files changed, 61 insertions(+), 60 deletions(-)