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[176.170.216.159]) by smtp.gmail.com with ESMTPSA id dj18-20020a0560000b1200b0032d96dd703bsm8108495wrb.70.2023.10.23.09.10.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 23 Oct 2023 09:10:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [RFC PATCH 9/9] target/ppc: Use tcg_gen_sextract_tl Date: Mon, 23 Oct 2023 18:09:44 +0200 Message-ID: <20231023160944.10692-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231023160944.10692-1-philmd@linaro.org> References: <20231023160944.10692-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Nicholas Piggin --- RFC: Please double-check 32/64 & bits --- target/ppc/translate.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c6e1f7c2ca..1370db9bd5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2892,13 +2892,7 @@ static void gen_slw(DisasContext *ctx) t0 = tcg_temp_new(); /* AND rS with a mask that is 0 when rB >= 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif + tcg_gen_sextract_tl(t0, cpu_gpr[rB(ctx->opcode)], 5, 1); tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); t1 = tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); @@ -2956,13 +2950,7 @@ static void gen_srw(DisasContext *ctx) t0 = tcg_temp_new(); /* AND rS with a mask that is 0 when rB >= 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif + tcg_gen_sextract_tl(t0, cpu_gpr[rB(ctx->opcode)], 5, 1); tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); tcg_gen_ext32u_tl(t0, t0); t1 = tcg_temp_new(); @@ -2981,8 +2969,7 @@ static void gen_sld(DisasContext *ctx) t0 = tcg_temp_new(); /* AND rS with a mask that is 0 when rB >= 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); + tcg_gen_sextract_tl(t0, cpu_gpr[rB(ctx->opcode)], 6, 1); tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); t1 = tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); @@ -3071,8 +3058,7 @@ static void gen_srd(DisasContext *ctx) t0 = tcg_temp_new(); /* AND rS with a mask that is 0 when rB >= 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); + tcg_gen_sextract_tl(t0, cpu_gpr[rB(ctx->opcode)], 6, 1); tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); t1 = tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);