[24/35] tcg/loongarch64: Implement neg opcodes

Message ID	20231107024842.7650-25-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 24/35] tcg/loongarch64: Implement neg opcodes Date: Mon, 6 Nov 2023 18:48:31 -0800 Message-Id: <20231107024842.7650-25-richard.henderson@linaro.org> In-Reply-To: <20231107024842.7650-1-richard.henderson@linaro.org> References: <20231107024842.7650-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[01/35] accel/tcg: Move HMP info jit and info opcount code \| expand [01/35] accel/tcg: Move HMP info jit and info opcount code [02/35] tcg: Add C_N2_I1 [03/35] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a_i128 [04/35] util: Add cpuinfo for loongarch64 [05/35] tcg/loongarch64: Use cpuinfo.h [06/35] host/include/loongarch64: Add atomic16 load and store [07/35] accel/tcg: Remove redundant case in store_atom_16 [08/35] accel/tcg: Fix condition for store_atom_insert_al16 [09/35] tcg: Mark tcg_gen_op as noinline [10/35] tcg: Move tcg_gen_op* out of line [11/35] tcg: Move generic expanders out of line [12/35] tcg: Move 32-bit expanders out of line [13/35] tcg: Move 64-bit expanders out of line [14/35] tcg: Move vec_gen_* declarations to tcg-internal.h [15/35] tcg: Move tcg_gen_opN declarations to tcg-internal.h [16/35] tcg: Unexport tcg_gen_op_{i32,i64} [17/35] tcg: Move tcg_constant_ out of line [18/35] tcg: Move tcg_temp_new_, tcg_global_mem_new_ out of line [19/35] tcg: Move tcg_temp_free_* out of line [20/35] tcg/mips: Split out tcg_out_setcond_int [21/35] tcg/mips: Always implement movcond [22/35] tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} [23/35] tcg/mips: Implement neg opcodes [24/35] tcg/loongarch64: Implement neg opcodes [25/35] tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} [26/35] tcg: Don't free vector results [27/35] tcg/optimize: Pipe OptContext into reset_ts [28/35] tcg/optimize: Split out cmp_better_copy [29/35] tcg/optimize: Optimize env memory operations [30/35] tcg: Eliminate duplicate env store operations [31/35] tcg/optimize: Split out arg_new_constant [32/35] tcg: Canonicalize subi to addi during opcode generation [33/35] tcg/optimize: Canonicalize subi to addi during optimization [34/35] tcg/optimize: Canonicalize sub2 with constants to add2 [35/35] tcg/sparc64: Implement tcg_out_extrl_i64_i32

Message ID

20231107024842.7650-25-richard.henderson@linaro.org

State

New

Headers

Received-SPF: pass (google.com: domain of
 qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as
 permitted sender) client-ip=209.51.188.17;
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 24/35] tcg/loongarch64: Implement neg opcodes
Date: Mon,  6 Nov 2023 18:48:31 -0800
Message-Id: <20231107024842.7650-25-richard.henderson@linaro.org>
In-Reply-To: <20231107024842.7650-1-richard.henderson@linaro.org>
References: <20231107024842.7650-1-richard.henderson@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Received-SPF: pass client-ip=2607:f8b0:4864:20::32e;
 envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
 DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
 RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,
 T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org

Series

[01/35] accel/tcg: Move HMP info jit and info opcount code | expand

Commit Message

Richard Henderson Nov. 7, 2023, 2:48 a.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target.h     | 4 ++--
 tcg/loongarch64/tcg-target.c.inc | 9 +++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 486898c2d3..189997644a 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -119,7 +119,7 @@  typedef enum {
 #define TCG_TARGET_HAS_bswap16_i32      1
 #define TCG_TARGET_HAS_bswap32_i32      1
 #define TCG_TARGET_HAS_not_i32          1
-#define TCG_TARGET_HAS_neg_i32          0
+#define TCG_TARGET_HAS_neg_i32          1
 #define TCG_TARGET_HAS_andc_i32         1
 #define TCG_TARGET_HAS_orc_i32          1
 #define TCG_TARGET_HAS_eqv_i32          0
@@ -153,7 +153,7 @@  typedef enum {
 #define TCG_TARGET_HAS_bswap32_i64      1
 #define TCG_TARGET_HAS_bswap64_i64      1
 #define TCG_TARGET_HAS_not_i64          1
-#define TCG_TARGET_HAS_neg_i64          0
+#define TCG_TARGET_HAS_neg_i64          1
 #define TCG_TARGET_HAS_andc_i64         1
 #define TCG_TARGET_HAS_orc_i64          1
 #define TCG_TARGET_HAS_eqv_i64          0
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index ae13c1f666..a588fb3085 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1441,6 +1441,13 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_neg_i32:
+        tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
+        break;
+    case INDEX_op_neg_i64:
+        tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1);
+        break;
+
     case INDEX_op_mul_i32:
         tcg_out_opc_mul_w(s, a0, a1, a2);
         break;
@@ -2076,6 +2083,8 @@  static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extrl_i64_i32:
     case INDEX_op_extrh_i64_i32:
     case INDEX_op_ext_i32_i64:
+    case INDEX_op_neg_i32:
+    case INDEX_op_neg_i64:
     case INDEX_op_not_i32:
     case INDEX_op_not_i64:
     case INDEX_op_extract_i32:

[24/35] tcg/loongarch64: Implement neg opcodes

Commit Message

Patch