diff mbox series

[PULL,78/85] target/hppa: Add unwind_breg to CPUHPPAState

Message ID 20231107030407.8979-79-richard.henderson@linaro.org
State New
Headers show
Series [PULL,01/85] target/hppa: Include PSW_P in tb flags and mmu index | expand

Commit Message

Richard Henderson Nov. 7, 2023, 3:04 a.m. UTC 
Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/cpu.h       |  8 +++++++-
 target/hppa/cpu.c       |  1 +
 target/hppa/translate.c | 13 ++++++++++++-
 3 files changed, 20 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index ea8e7e99a4..144794d089 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -45,7 +45,7 @@ 
 #define MMU_IDX_TO_P(MIDX)          (((MIDX) - MMU_KERNEL_IDX) & 1)
 #define PRIV_P_TO_MMU_IDX(PRIV, P)  ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
+#define TARGET_INSN_START_EXTRA_WORDS 2
 
 /* No need to flush MMU_PHYS_IDX  */
 #define HPPA_MMU_FLUSH_MASK                             \
@@ -208,6 +208,12 @@  typedef struct CPUArchState {
     target_ulong cr_back[2]; /* back of cr17/cr18 */
     target_ulong shadow[7];  /* shadow registers */
 
+    /*
+     * During unwind of a memory insn, the base register of the address.
+     * This is used to construct CR_IOR for pa2.0.
+     */
+    uint32_t unwind_breg;
+
     /*
      * ??? The number of entries isn't specified by the architecture.
      * BTLBs are not supported in 64-bit machines.
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e1597ba8a5..04de1689d7 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -80,6 +80,7 @@  static void hppa_restore_state_to_opc(CPUState *cs,
     if (data[1] != (target_ulong)-1) {
         cpu->env.iaoq_b = data[1];
     }
+    cpu->env.unwind_breg = data[2];
     /*
      * Since we were executing the instruction at IAOQ_F, and took some
      * sort of action that provoked the cpu_restore_state, we can infer
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4102f5faf3..bcce65d587 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -44,6 +44,7 @@  typedef struct DisasCond {
 typedef struct DisasContext {
     DisasContextBase base;
     CPUState *cs;
+    TCGOp *insn_start;
 
     uint64_t iaoq_f;
     uint64_t iaoq_b;
@@ -234,6 +235,13 @@  void hppa_translate_init(void)
                                         "iasq_b");
 }
 
+static void set_insn_breg(DisasContext *ctx, int breg)
+{
+    assert(ctx->insn_start != NULL);
+    tcg_set_insn_start_param(ctx->insn_start, 2, breg);
+    ctx->insn_start = NULL;
+}
+
 static DisasCond cond_make_f(void)
 {
     return (DisasCond){
@@ -1324,6 +1332,8 @@  static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
     TCGv_i64 ofs;
     TCGv_i64 addr;
 
+    set_insn_breg(ctx, rb);
+
     /* Note that RX is mutually exclusive with DISP.  */
     if (rx) {
         ofs = tcg_temp_new_i64();
@@ -4458,7 +4468,8 @@  static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b);
+    tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0);
+    ctx->insn_start = tcg_last_op();
 }
 
 static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)