From patchwork Tue Nov 21 14:46:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 745695 Delivered-To: patch@linaro.org Received: by 2002:a5d:5052:0:b0:32d:baff:b0ca with SMTP id h18csp1914965wrt; Tue, 21 Nov 2023 06:47:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IF0B4Ze0eihq4lyONjoaFaMHQ9YoT2+SivRExDHyoIbx9kYRMUhsJmK+2cl1Cp7a4nKAKi4 X-Received: by 2002:ac8:7201:0:b0:423:7326:515f with SMTP id a1-20020ac87201000000b004237326515fmr1254096qtp.11.1700578021165; Tue, 21 Nov 2023 06:47:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700578021; cv=none; d=google.com; s=arc-20160816; b=sHDO4ZqjE3rI81EpARDpZ1Wm7svGPqvBcxLqZpstrLAJnGZ9MuiB+OqImCbeMvAVSl AIVzGHifPuMhCmcxnJDBWH5q2YiAH6sDAoFgAJGtGLM3lh424IF1qW56Kt57zGdYBH/j Y7+PhZjReOJDAR0QjnhsoSZZnpQdyzVHQV61Gvl7wgBmBtr2AFBIfIRrU4JjcworderM 0qZKdTStOWJcFaQ4UuIeA57i46pZFieZ2qNY6+zjiprZsyBHfhr25d5Shww9vGJ3saEf DCVkqoSRnil8m/2C6hwe74AGYpAJthmD1xRbD0lU3K0qIa4yw1pi2AM4YQGQDe148IQT StDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=Z/Q0Ze2x0fQAFBtYAYpPfU903dcHJSY8SIbcnM+aFf8=; fh=H2AmuqulvQE+T5zu97MCEUC3z9wF9NssS7895NhR/+c=; b=TCsfXVfai7agSdXk3jdEKuF/pokJ20w3UVfbnNq1k2y1IIVlBdUN5zh15M434xcBOy CAb/cyra6Qb8BIV050Je5dIv3lM65ffo+OxsCGXtg2+EByL3patvfees41TRuHqcFAye 2fMqwxdnhz4nLPeBIBGr9+/gWhCIafRf8lInE9d8p6PB/sArxMTn+Pg2e670tP3mEnY0 JcoGjAeCuQFm6zzFwA9TAgBNzgsh1GR4wj1gcVV7b1mDo2CN4g6dcF9kUI1id20uChTb nD6DR6UgawYT5LHnKatCX0JPsBRIbu2AlS4Ilmp7ghbAvqSZ9g22vzaf7PKvnhlm4+BQ 5vRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IybLorbY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u3-20020ac858c3000000b0040551209eb5si9563376qta.585.2023.11.21.06.47.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Nov 2023 06:47:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IybLorbY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5S14-0000Ig-GC; Tue, 21 Nov 2023 09:46:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5S0x-0000IC-SU for qemu-devel@nongnu.org; Tue, 21 Nov 2023 09:46:14 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5S0u-0000mx-3d for qemu-devel@nongnu.org; Tue, 21 Nov 2023 09:46:11 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-32f8441dfb5so4346880f8f.0 for ; Tue, 21 Nov 2023 06:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700577966; x=1701182766; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=Z/Q0Ze2x0fQAFBtYAYpPfU903dcHJSY8SIbcnM+aFf8=; b=IybLorbYvvGgpeOErkXwOJ4pit3j75PI03VFLK5oMxfehRRMtPARpTqPDPeek0Pt0m tZIcgFYGVpFM3Sq8X39/9B/Gz0usnWXUxXv6Wz4N0Ifxsh5H00PoBsxsZs2uJ1Pk4tqy S5MWPcNOWCpwbRfeC2U9sFhnLLS38mCF8Mg3xsbvqAeKumBwXaq29GVEuUDLjqUbo0kA cv2meTzC+1wLSan9n4EI/SUkivynNYXI+8eUzJlav+dWFLnCgR3i4YY571X4PLUsO2Cc shSML4uCJsI3SVYMbd4wGaDlmkHkNov5SGcNAxLxcTp5Jxhm3HhFIoeme4uPpjgm5fvR EdRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700577966; x=1701182766; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Z/Q0Ze2x0fQAFBtYAYpPfU903dcHJSY8SIbcnM+aFf8=; b=IktRoyubf3pqD63y32kvy0akZn9vUGufH/WY3SfSl/7gja+PcVGgdDQ9BQpVriqjQC UuFuQYOWbT93BzbrqjzmM9o3aJKE9yxU5C1bfCjl8czUiFBUQ4CLbunylYJOX9brniUv 5YUFPL2Vu2N+7do5Dl96BFymVsw6jtRnWa/S/ydV6HQKwlKNtC+qgO+HLYZ5S3aWh22q 6owv46BdHneIWaoQab79wB2C0sYSVCyWcQIkhVdHffdS4EbOuH+mmFAH3wYXSk+hwCho /ZFQF8WDUxPH6Ts1A92/LcWcuyvt07Z+RJDedxympIIa3f8MuLFZ+fKLi4Ni65hxOvfF Oq/A== X-Gm-Message-State: AOJu0Yw0u0McKEFXMXQXmP1K4Z+EYLX6p0MiiF/zUQ2y20Q6v6GtUdH6 wrjuJ4u/EdtxtTc/Zdalb/AMUUL1GPmA2rV9xOA= X-Received: by 2002:a05:6000:43:b0:32f:c3d0:89db with SMTP id k3-20020a056000004300b0032fc3d089dbmr7218859wrx.27.1700577966334; Tue, 21 Nov 2023 06:46:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d10-20020a5d644a000000b003316db2d48dsm12911463wrw.34.2023.11.21.06.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 06:46:06 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only Date: Tue, 21 Nov 2023 14:46:05 +0000 Message-Id: <20231121144605.3980419-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I happened to notice this reading through the Arm ARM recently. This is technically a bug, but you'll only notice it if you deliberately look at what should be an unimplemented register to see if it UNDEFs, so I don't think it's worth either putting in 8.2 or backporting to stable. --- target/arm/debug_helper.c | 23 +++++++++++++++-------- target/arm/helper.c | 35 +++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cbfba532f50..83d2619080f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1026,14 +1026,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_RW, .accessfn = access_tda, .type = ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, - .access = PL2_RW, .accessfn = access_tda, - .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit @@ -1062,6 +1054,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) }, }; +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo debug_aa32_el1_reginfo[] = { + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, + .access = PL2_RW, .accessfn = access_tda, + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, +}; + static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { /* 64 bit access versions of the (dummy) debug registers */ { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, @@ -1207,6 +1211,9 @@ void define_debug_regs(ARMCPU *cpu) assert(ctx_cmps <= brps); define_arm_cp_regs(cpu, debug_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, debug_aa32_el1_reginfo); + } if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); diff --git a/target/arm/helper.c b/target/arm/helper.c index ff1970981ee..bf26b995171 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5681,20 +5681,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_RAW, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, - { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, - .access = PL2_RW, - .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, - { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, - .writefn = dacr_write, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, - .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, @@ -5729,6 +5715,24 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo v8_aa32_el1_reginfo[] = { + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, + .access = PL2_RW, + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, + { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, + .writefn = dacr_write, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, +}; + static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) { ARMCPU *cpu = env_archcpu(env); @@ -8699,6 +8703,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); + } for (i = 4; i < 16; i++) { /*