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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 12/33] hw/cpu/arm: Create MPCore container in QOM parent Date: Tue, 12 Dec 2023 17:29:12 +0100 Message-ID: <20231212162935.42910-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the memory region container creation to the abstract QOM parent. Children set the region size via the class 'container_size' field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater --- include/hw/cpu/cortex_mpcore.h | 10 ++++++++-- hw/cpu/a15mpcore.c | 17 ++++++++--------- hw/cpu/a9mpcore.c | 18 +++++++++--------- hw/cpu/cortex_mpcore.c | 14 ++++++++++++++ 4 files changed, 39 insertions(+), 20 deletions(-) diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index 4084c6003a..1d94c8769d 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -30,14 +30,22 @@ #define TYPE_CORTEX_MPCORE_PRIV "cortex_mpcore_priv" OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV) +/** + * CortexMPPrivClass: + * @container_size - size of the device's MMIO region + */ struct CortexMPPrivClass { SysBusDeviceClass parent_class; DeviceRealize parent_realize; + + uint64_t container_size; }; struct CortexMPPrivState { SysBusDevice parent_obj; + + MemoryRegion container; }; #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" @@ -47,7 +55,6 @@ struct A9MPPrivState { CortexMPPrivState parent_obj; uint32_t num_cpu; - MemoryRegion container; uint32_t num_irq; A9SCUState scu; @@ -65,7 +72,6 @@ struct A15MPPrivState { uint32_t num_cpu; uint32_t num_irq; - MemoryRegion container; GICState gic; }; diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 5a57145179..128941eb50 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -36,12 +36,8 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int level) static void a15mp_priv_initfn(Object *obj) { - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); A15MPPrivState *s = A15MPCORE_PRIV(obj); - memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); - sysbus_init_mmio(sbd, &s->container); - object_initialize_child(obj, "gic", &s->gic, gic_class_name()); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); } @@ -51,6 +47,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); A15MPPrivState *s = A15MPCORE_PRIV(dev); + CortexMPPrivState *c = CORTEX_MPCORE_PRIV(dev); DeviceState *gicdev; SysBusDevice *gicsbd; Error *local_err = NULL; @@ -133,20 +130,20 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) * 0x5600-0x57ff -- GIC virtual interface control for CPU 3 * 0x6000-0x7fff -- GIC virtual CPU interface */ - memory_region_add_subregion(&s->container, 0x1000, + memory_region_add_subregion(&c->container, 0x1000, sysbus_mmio_get_region(gicsbd, 0)); - memory_region_add_subregion(&s->container, 0x2000, + memory_region_add_subregion(&c->container, 0x2000, sysbus_mmio_get_region(gicsbd, 1)); if (has_el2) { - memory_region_add_subregion(&s->container, 0x4000, + memory_region_add_subregion(&c->container, 0x4000, sysbus_mmio_get_region(gicsbd, 2)); - memory_region_add_subregion(&s->container, 0x6000, + memory_region_add_subregion(&c->container, 0x6000, sysbus_mmio_get_region(gicsbd, 3)); for (i = 0; i < s->num_cpu; i++) { hwaddr base = 0x5000 + i * 0x200; MemoryRegion *mr = sysbus_mmio_get_region(gicsbd, 4 + s->num_cpu + i); - memory_region_add_subregion(&s->container, base, mr); + memory_region_add_subregion(&c->container, base, mr); } } } @@ -168,6 +165,8 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass); + cc->container_size = 0x8000; + device_class_set_parent_realize(dc, a15mp_priv_realize, &cc->parent_realize); device_class_set_props(dc, a15mp_priv_properties); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d59e49126b..08346b0049 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -30,9 +30,6 @@ static void a9mp_priv_initfn(Object *obj) { A9MPPrivState *s = A9MPCORE_PRIV(obj); - memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); - object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); @@ -47,6 +44,7 @@ static void a9mp_priv_initfn(Object *obj) static void a9mp_priv_realize(DeviceState *dev, Error **errp) { CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev); + CortexMPPrivState *c = CORTEX_MPCORE_PRIV(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); A9MPPrivState *s = A9MPCORE_PRIV(dev); DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; @@ -134,21 +132,21 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) * 0x0700-0x0fff -- nothing * 0x1000-0x1fff -- GIC Distributor */ - memory_region_add_subregion(&s->container, 0, + memory_region_add_subregion(&c->container, 0, sysbus_mmio_get_region(scubusdev, 0)); /* GIC CPU interface */ - memory_region_add_subregion(&s->container, 0x100, + memory_region_add_subregion(&c->container, 0x100, sysbus_mmio_get_region(gicbusdev, 1)); - memory_region_add_subregion(&s->container, 0x200, + memory_region_add_subregion(&c->container, 0x200, sysbus_mmio_get_region(gtimerbusdev, 0)); /* Note that the A9 exposes only the "timer/watchdog for this core" * memory region, not the "timer/watchdog for core X" ones 11MPcore has. */ - memory_region_add_subregion(&s->container, 0x600, + memory_region_add_subregion(&c->container, 0x600, sysbus_mmio_get_region(mptimerbusdev, 0)); - memory_region_add_subregion(&s->container, 0x620, + memory_region_add_subregion(&c->container, 0x620, sysbus_mmio_get_region(wdtbusdev, 0)); - memory_region_add_subregion(&s->container, 0x1000, + memory_region_add_subregion(&c->container, 0x1000, sysbus_mmio_get_region(gicbusdev, 0)); /* Wire up the interrupt from each watchdog and timer. @@ -183,6 +181,8 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass); + cc->container_size = 0x2000; + device_class_set_parent_realize(dc, a9mp_priv_realize, &cc->parent_realize); device_class_set_props(dc, a9mp_priv_properties); } diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c index 7d3796bd69..0c12f99610 100644 --- a/hw/cpu/cortex_mpcore.c +++ b/hw/cpu/cortex_mpcore.c @@ -7,13 +7,27 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/cpu/cortex_mpcore.h" +static void cortex_mpcore_priv_instance_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + CortexMPPrivState *s = CORTEX_MPCORE_PRIV(obj); + CortexMPPrivClass *k = CORTEX_MPCORE_PRIV_GET_CLASS(obj); + + assert(k->container_size > 0); + memory_region_init(&s->container, obj, + "mpcore-priv-container", k->container_size); + sysbus_init_mmio(sbd, &s->container); +} + static const TypeInfo cortex_mpcore_types[] = { { .name = TYPE_CORTEX_MPCORE_PRIV, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(CortexMPPrivState), + .instance_init = cortex_mpcore_priv_instance_init, .class_size = sizeof(CortexMPPrivClass), .abstract = true, },