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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id i12-20020adff30c000000b00336b8461a5esm2980486wro.88.2024.01.09.10.09.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:09:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 01/14] target/arm/cpu: Simplify checking A64_MTE bit in FEATURE_ID register Date: Tue, 9 Jan 2024 19:09:16 +0100 Message-ID: <20240109180930.90793-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_isar_feature(aa64_mte, cpu) is testing a AArch64-only ID register. The ARM_FEATURE_AARCH64 check is redundant. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c8b787482..c828b333c9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1690,8 +1690,7 @@ void arm_cpu_post_init(Object *obj) } #ifndef CONFIG_USER_ONLY - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && - cpu_isar_feature(aa64_mte, cpu)) { + if (cpu_isar_feature(aa64_mte, cpu)) { object_property_add_link(obj, "tag-memory", TYPE_MEMORY_REGION, (Object **)&cpu->tag_memory,