From patchwork Thu Jan 11 11:04:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 761795 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2335282wrz; Thu, 11 Jan 2024 03:05:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEpmjDC7DNEs3Vmi+uQU1CoM6xvzIlHs8vNZaodPKohGShA8mmoL3XKjsezv/eozgUxaauO X-Received: by 2002:a05:6214:1d23:b0:681:854:e713 with SMTP id f3-20020a0562141d2300b006810854e713mr861859qvd.84.1704971145103; Thu, 11 Jan 2024 03:05:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704971145; cv=none; d=google.com; s=arc-20160816; b=TNE3ggOjuZhjSOeZa9mVuW5YaXr3w56HPVbKW1TQjQwLcWnLUbiwrcsEwfFwQd8l+X 9p8hgIGC43Wxg5ucyi7bY9CLq3DCmtSL1nhYenT9ml/2J3VG+ddIzfQRyprfXvoprEx+ Vr+fal6dPUQxr1VxXZJXyboeOQEexH/GjUhFJraFtO0ohiy0K5V9vgZoQM4Q0D0VJdfx 3xcUoPUPr8vF91BruMwhFPm6egCcwIWUljauFimVviqLt55HHRCYc2u21E97+OtKtprm tPIbEdJW59Q+0LzAK5LYZczPWqjuTz1PSjHtWrs3l+sJvah464VFWzN9YzLtFMkqZdiK 4BMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CaJ0lo5TmAF8BFZ0QGqs81rse4aATjl1O9jO7ww+ztg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=lKaggBhcCvZteXRv4ENOXYN3v9jmJhkIwC2t02ioOurVfIVKUxurpKIKIrvQigLNXm W1suDvZ9FOxoxRreVRe85FGwbniFW6Ii0DXuVWv7kZcON0yxKu1zLPRza1zHMWCJHfy9 sfT2qwTQNclUPswUrq+398FxZbtUVbtyifXQNy0yDBkMmNgW8qRFkcHNXCe+ltk/qr2g plHPGAfA3eOABiyUEIQcdMbp8tpOCxc64znBq14g8nS81EGjjUMspGASsYzyuQhnjlIl eH/YVdBMdxmfSK7I/NE/mwHtf8AW14Qcot72K38elo0Yl/A0rCvuARLxL5vJEcELTKna 21ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cRCaNUQn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g14-20020a0cdf0e000000b0067f26df4442si568025qvl.150.2024.01.11.03.05.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Jan 2024 03:05:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cRCaNUQn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rNss9-0001MA-O9; Thu, 11 Jan 2024 06:05:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rNss5-0001KC-CN for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rNss2-0004NP-Qs for qemu-devel@nongnu.org; Thu, 11 Jan 2024 06:05:13 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40e60e13762so3186585e9.2 for ; Thu, 11 Jan 2024 03:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971109; x=1705575909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CaJ0lo5TmAF8BFZ0QGqs81rse4aATjl1O9jO7ww+ztg=; b=cRCaNUQntyq4UDLQnlhaDdISitRxAwTafcAcikJzadIrgofqFIt+YcuTo6tOUJf/la JqCCuUbuLMeKisjZzxi0dwo/1EMCwImV50yqvh1bnXrqfjCsjECb8ziECiwxMqlLXdfr aiLQvNWIv7ucyLAK1hRg8/B2COMcWJoVUvt4d3UPL0vO/304tKnWkd47rT1TbK59pAdS 488Y+06F+aag8Juz0bQ/QEKig/OEbyZr1AmTiOcL6lcnSTgPiRPLXBfs1O10jgZY7qRr VFtMSyiMd2PUnCyPHlz/M/iX5sL9tdn5IPg/3UuWn6Hd/FyNBokYNqP0+wv1Col7/78Q slow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971109; x=1705575909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CaJ0lo5TmAF8BFZ0QGqs81rse4aATjl1O9jO7ww+ztg=; b=Y5bUMBjo9STw9GEnWsclR1uVimjv7qsmSDJenOX3ldXRzaKf5qp3hbERidhzft7fW6 nJlHlvODG1+z37irsbUFgHkconHyU6xf52KbuV978dN5dX6CjZ9nxT4bcbYL7Y3cTdRX eOPaziVb9Qu+0c+UL0Qx1Eiv7lnYxiSkhpeetdyz5lmyoB43iyWhkQ3j/VJZZbFsBc1S zZqRZ3pAxOvi02Lr8fZz8ZTCkl7TDq43UbDIUsFkKSFhaUzYDb/+AVCBiBYp6N8URI4Z lRxwdUDM3ElGB3iuAEi93BBuieiFceKd5LH14pcBJ+jJN0tQZq1vlsGb1RB2BEVU8M3r 8YjA== X-Gm-Message-State: AOJu0YxrUK7aOmvvVgr7EulpTXfhnBUCF5agFAQEahTnIYqZT97KW2sz UAJMPiWqYRoHg6mAf58Mpcy39uzx3J70/dmGDHLc4tF6p2g= X-Received: by 2002:a05:600c:2158:b0:40e:526f:a110 with SMTP id v24-20020a05600c215800b0040e526fa110mr142562wml.107.1704971108972; Thu, 11 Jan 2024 03:05:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property Date: Thu, 11 Jan 2024 11:04:28 +0000 Message-Id: <20240111110505.1563291-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Samuel Tardieu Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits. This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-id: 20240106181503.1746200-2-sam@rfc1149.net Suggested-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 50f9a973a2e..404a445138a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = { static Property props_nvic[] = { /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), + /* + * Number of the maximum priority bits that can be used. 0 means + * to use a reasonable default. + */ + DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0), DEFINE_PROP_END_OF_LIST() }; @@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) /* include space for internal exception vectors */ s->num_irq += NVIC_FIRST_IRQ; - s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + if (s->num_prio_bits == 0) { + /* + * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1 + * and 8 bits otherwise. + */ + s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + } else { + uint8_t min_prio_bits = + arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 3 : 2; + if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) { + error_setg(errp, + "num-prio-bits %d is outside " + "NVIC acceptable range [%d-8]", + s->num_prio_bits, min_prio_bits); + return; + } + } /* * This device provides a single memory region which covers the