From patchwork Mon Jan 22 14:55:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 764646 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1140887wrx; Mon, 22 Jan 2024 06:58:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IHSqhkL879R5BvT0KKa4DX9No1safrHGCPOIf6bzgBUqLoGZ6KZWKRrDbyiZOIGbQ2JAOWg X-Received: by 2002:a05:6214:dcb:b0:685:9815:eaf3 with SMTP id 11-20020a0562140dcb00b006859815eaf3mr4812704qvt.24.1705935503281; Mon, 22 Jan 2024 06:58:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705935503; cv=none; d=google.com; s=arc-20160816; b=S6M7kvBOo1HHDxDclNt41xn5Z15HeClAgKhn+EGIOh0vl4gg66JzcBjG+nEtHiWPDO Y+txrFj2eA+qf47oQ5+E27f25Yekqfgrj0iGr5u5V0BoTDN3m7PJ9YEBm6050M1VbhON FYvGk3mZ/T3evIWRNkhAKUcjgEhVJPqqJt0nI9JCDTtd6sKO9CMx9ie5lxrJeI937983 yGZb+p+u3137/5qusYC2Dw9icP7QNJxwJR83gub5AD4dPMvmlvnt6biir6Gp0EAOjJd2 rd+L89lOmIa59DiLfhW3hxs9uvQJp1VSKp81CaUlkJLi816SKwYRecH3oEIoarWhPF0Z HJDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wnacmpzMiYYkR6luXZ5eIHuYPHULuf9iQCNwzs9Z38M=; fh=mGQIuaf4A7RZOxcauYqguCwKMqzWt70hd4nAkQm0M6A=; b=IBfF8JaS29YGSzL5e/ciewxZsVP6WlbM6uY1/6lD0ohBK7YORCvZgg/S6bpB8OiBSk /xpkINWc/VUZAIVfT8ZV+wweDLiRzG5NxeDTxbqeJUJJzcUUcI3Jdh4QGMhh2E7hRAvJ XSEuYD9bgGgT1VhvP33JL/mvFUscdZjb7s0u0Mogn4xZkZV4RNKdvRMKFbsDpfCerYPn bMF0bc1mME5NiRjcOdM/lRAeeCzRdGjdL4ov1qmx5ZPim61DGQWo9wY/UbU2KL+hI/ta pmf9pyJ2Cz655c2x+I3AyfFWM3o18/3do68SDcAvTZW+fwRQeaZXEYfAREXAaosf3edI bbmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8QVF3L7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a12-20020a0ce38c000000b0067f9474ef53si5797918qvl.368.2024.01.22.06.58.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jan 2024 06:58:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8QVF3L7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rRvjB-0007HA-IW; Mon, 22 Jan 2024 09:56:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRviw-00075V-2g for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:56:32 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rRvil-0008M8-GQ for qemu-devel@nongnu.org; Mon, 22 Jan 2024 09:56:29 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3392b15ca41so1078603f8f.0 for ; Mon, 22 Jan 2024 06:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705935378; x=1706540178; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wnacmpzMiYYkR6luXZ5eIHuYPHULuf9iQCNwzs9Z38M=; b=P8QVF3L7tdXQrFuB02r4CP1LREp/BeUdvbptYSCBvGzJzHcuUGt2cvYvsotKs3SMSb IKaX9+SQDf8U1flJPlbeLb0UDCWoG3gFDEcmiwVigXgNZgOdvGoq+gWLzEfwxOP9QHxq 7FuPoZwjYFJYZrAizTPtDeGcyeccx72bgcVwZtJ1ZrU/Jqo4trqm7iLHLliskzbCIBOX WlsraE+aEAb5+nfJ7qfriyvZHvw2hSlP16ekMnCSgqcTq4DCRJBvubSqWsX2pOpp3ipQ RPQEy8lYyT3e0MKN0BbN4kPBHg02/Paiyxs62t9Zo0P2ouuVw7Q0p2YFRLjFDxSMayJP dE3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705935378; x=1706540178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wnacmpzMiYYkR6luXZ5eIHuYPHULuf9iQCNwzs9Z38M=; b=Cb+Z0FIH/uTbt6//gQffShBL+cWb4l3IrfVdlWMfT/fROsadXTvu0fS6rWd/5PSfnW Ca2WTaOSrQ2YBG8GSFRIiJuwZes4QWpVGp6GhEr4jCjvvYTqvRYw8Y2iKAfFU99QjVeS w4oSi3rw7EFkBHY5n3+ojfXVU69gsLrAaflo9liYmp++JR/G+3vCI36yI7uTs1/jDaxq M5+qi/YucN7qJjMpBOZhwSCGuOv3DZ+wmRd4t5rPnxlqRtXT3Q6/JTezOpgcJUWFIK8S 38VzxogVgWtaMbqfEBHpf494M0RpJGM1aj62euJsL9dh/LLK6usu+iAYyHyllUbJsR5o amwg== X-Gm-Message-State: AOJu0YwrZoaRe703fAR9GeYdHyErc3TQivgjG5hNVlAMii8EpdnBZuA5 nnBZzpjl3p/TA0tLBWxhqcQC/m42GNyA9SQeZZdz9Dz+R8kg2DxQrlUyB+CDLpU= X-Received: by 2002:a5d:6a12:0:b0:337:4f04:933c with SMTP id m18-20020a5d6a12000000b003374f04933cmr2124774wru.54.1705935378000; Mon, 22 Jan 2024 06:56:18 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id c6-20020a5d4f06000000b0033930068ca8sm4244050wru.21.2024.01.22.06.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 06:56:14 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 8CF035F7AE; Mon, 22 Jan 2024 14:56:11 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= , Michael Rolnik , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Laurent Vivier , kvm@vger.kernel.org, Yoshinori Sato , Pierrick Bouvier , Palmer Dabbelt , Liu Zhiwei , Laurent Vivier , Yanan Wang , qemu-ppc@nongnu.org, Weiwei Li , qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Peter Maydell , Alexandre Iooss , John Snow , Mahmoud Mandour , Wainer dos Santos Moschetta , Richard Henderson , Ilya Leoshkevich , Alistair Francis , David Woodhouse , Cleber Rosa , Beraldo Leal , Bin Meng , Nicholas Piggin , Aurelien Jarno , Daniel Henrique Barboza , Daniel Henrique Barboza , Thomas Huth , David Hildenbrand , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , Song Gao , Eduardo Habkost , Brian Cain , Paul Durrant , Akihiko Odaki Subject: [PATCH v3 07/21] target/riscv: Use GDBFeature for dynamic XML Date: Mon, 22 Jan 2024 14:55:56 +0000 Message-Id: <20240122145610.413836-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240122145610.413836-1-alex.bennee@linaro.org> References: <20240122145610.413836-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Message-Id: <20240103173349.398526-29-alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com> Signed-off-by: Alex Bennée --- target/riscv/cpu.h | 5 +-- target/riscv/cpu.c | 4 +-- target/riscv/gdbstub.c | 79 +++++++++++++++++++----------------------- 3 files changed, 40 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d269d53e59c..8731af50718 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-properties.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" @@ -440,8 +441,8 @@ struct ArchCPU { CPURISCVState env; - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7ee4f8520f9..a488361626f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1672,9 +1672,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) RISCVCPU *cpu = RISCV_CPU(cs); if (strcmp(xmlname, "riscv-csr.xml") == 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 365040228a1..76b72a95954 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -214,13 +214,14 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) return 0; } -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - GString *s = g_string_new(NULL); + GDBFeatureBuilder builder; riscv_csr_predicate_fn predicate; + const char *name; int bitsize = 16 << mcc->misa_mxl_max; int i; @@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) bitsize = 64; } - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, + "org.gnu.gdb.riscv.csr", "riscv-csr.xml", + base_reg); for (i = 0; i < CSR_TABLE_SIZE; i++) { if (env->priv_ver < csr_ops[i].min_priv_ver) { @@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) } predicate = csr_ops[i].predicate; if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "", base_reg + i); + + gdb_feature_builder_append_reg(&builder, name, bitsize, i, + "int", NULL); } } - g_string_append_printf(s, ""); - - cpu->dyn_csr_xml = g_string_free(s, false); + gdb_feature_builder_end(&builder); #if !defined(CONFIG_USER_ONLY) env->debugger = false; #endif - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) { RISCVCPU *cpu = RISCV_CPU(cs); - GString *s = g_string_new(NULL); - g_autoptr(GString) ts = g_string_new(""); + GDBFeatureBuilder builder; int reg_width = cpu->cfg.vlen; - int num_regs = 0; int i; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, + "org.gnu.gdb.riscv.vector", "riscv-vector.xml", + base_reg); /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "%s", vec_lanes[i].id); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + gdb_feature_builder_append_tag( + &builder, "", + vec_lanes[i].id, vec_lanes[i].gdb_type, count); } /* Define unions */ - g_string_append_printf(s, ""); + gdb_feature_builder_append_tag(&builder, ""); for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - vec_lanes[i].id); + gdb_feature_builder_append_tag(&builder, + "", + vec_lanes[i].suffix, vec_lanes[i].id); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(&builder, ""); /* Define vector registers */ for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - num_regs++; + gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), + reg_width, i, "riscv_vector", "vector"); } - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); - cpu->dyn_vreg_xml = g_string_free(s, false); - return num_regs; + return &cpu->dyn_vreg_feature; } void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { - int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg), + ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs, "riscv-vector.xml", 0); } switch (mcc->misa_mxl_max) { @@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } if (cpu->cfg.ext_zicsr) { - int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs, "riscv-csr.xml", 0); } }