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[PULL,24/35] target/arm: The Cortex-R52 has a read-only CBAR

Message ID 20240215173538.2430599-25-peter.maydell@linaro.org
State Accepted
Commit fe31d6c72d0046eb633db51dc1d8fb9b231d270f
Headers show
Series [PULL,01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC | expand

Commit Message

Peter Maydell Feb. 15, 2024, 5:35 p.m. UTC 
The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register.  Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
---
 target/arm/tcg/cpu32.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 11253051156..311d654cdce 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -809,6 +809,7 @@  static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     cpu->midr = 0x411fd133; /* r1p3 */
     cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034023;