From patchwork Thu Feb 15 17:35:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 772918 Delivered-To: patch@linaro.org Received: by 2002:adf:9dc2:0:b0:33b:4db1:f5b3 with SMTP id q2csp953538wre; Thu, 15 Feb 2024 09:37:26 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVYZdKak61dShyDCPqaqOIm9NZizMUq+qL9DN5qlSBfPXBeNEljTraZuI4613Iqsbencv0MkH68l4dtx12FCnmV X-Google-Smtp-Source: AGHT+IGHYSboIT6m4qLA5/NcmASc+GO0r4rTVVj0gsFqHGliyisyEjimVkCG9GMorVubVI7M6FYL X-Received: by 2002:a25:8d0d:0:b0:dcb:ef22:3869 with SMTP id n13-20020a258d0d000000b00dcbef223869mr2165137ybl.16.1708018646250; Thu, 15 Feb 2024 09:37:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1708018646; cv=none; d=google.com; s=arc-20160816; b=HiQQxgha2k94EO5eSRSkZR3kjjnswmukHYBBWOeUyCHXHGWg01ExXg3NcOk3VMmYzg tf8G6laIlkmQGmoAe1CcpWbQOmqmb1jRE3V6bFKmQ7a9CzSXkwBySE15ov0TET9LvqqT MK8RbOLaB1QR2aC7efG94ufYLb9LfwLE7OuOdUycbV/uZJy6OeeGwG/X8fFzt6c1EJXH sCJxbLWh1YQg0+eGnTY8HMjopeKT8/HmuEWhfzC2OucVok13XK3snZomYmn6BcEochGD sNmaBKFAkO1WFa2YweOxb6BdhWSOS1Yg2nU/Sgk8vZLIxY9wf54Uerh69H6Wb3Q5rBM/ yKWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R5btJS3y3hUR8gjDhf2ty8AwSTtFlSAZAgw0FD5O3yo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ZMKYfiEUK9Yi2cwSYehEZnfuf6YFhBoFvOX/qZUSRGZIH3yrNUfPkwnV/x5GfzWd+m hdagwUAOTK72hyfuKwRlyCEKqTDL+nWgwbVFVYJvO7PjOI0a3zRw5H3tKwSuIXjx8FcO yCMtII2xFJqHYzH/TH3Wd7y8qPn/9retJQll8A2bFHIv2TOEH3y/TsKpqs46VPxgpXXU OueRoHLq1UExO1AvRE7N9Qpdx97VV7fNgMIbybZgyPnpaC3CzfJCSAsTssDdPSPeO1dN wKKohieTGtkhV4xAvs+ZH6a0rV5v0AsSJYTqp0M041HD3T4QeBCzrOaf/bAnkbtXnIJO +9SQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v81wawKS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s14-20020a05620a16ae00b0078715778c95si1887054qkj.42.2024.02.15.09.37.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 Feb 2024 09:37:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v81wawKS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rafer-0000OZ-33; Thu, 15 Feb 2024 12:36:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rafeH-0007wn-Gi for qemu-devel@nongnu.org; Thu, 15 Feb 2024 12:35:49 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rafeC-0003uZ-G2 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 12:35:49 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-33ce55ab993so632595f8f.1 for ; Thu, 15 Feb 2024 09:35:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708018542; x=1708623342; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=R5btJS3y3hUR8gjDhf2ty8AwSTtFlSAZAgw0FD5O3yo=; b=v81wawKSWPSx2yYlEDrGwDxMYp9XisLPmN9FHPwOQUXIpvJdCrDCdGSH4qNlUIuhLn 0GqYceh1sZ3+u0BBKByazZqbIDMq/VcTzOVFqGEjK6cPt1Fth3EKJDU9xoFYs9vxb01T At25RlSwMIe6027GtxxFk+5eao9xcJjyg3be9GF5GFSUH1zD/1p1jdoTSnKfeRE6gJJ/ c0qtXtHX/aGvDgQNf7+OflnrFmVqrmQsjl6WPw2N104rXa/jlRaOCtPXI0HyC7/uPZ1g P7ucsif9HPtU831RW3/y6nUX6/sw8uTSUV5W/MHc5G1S5ol6FCR3bHChkue2ohesh3Ss 77KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708018542; x=1708623342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R5btJS3y3hUR8gjDhf2ty8AwSTtFlSAZAgw0FD5O3yo=; b=OHLq0vmdHe1wVBurTQERIpDGoxabRYIXnQMGlaLgIL2FVYSkFjqPzYARYd6SWSupAy 0sXd4i5XGeBwaVGQXB+hhDgKYMM5d2KawG1L7eDaJdCXwp9ZD2pi0jhgigOuveVSSIaA s9791B1fa31ksMTjm1NpFUWljZqqQvIIYz+2+L79bRDx4pEBQrkWlnVHJ0l1X4slU7yR 9+s5eI/67kDQkSpARU6ZXvvQP7y1aKDUtZAXN9coElpz8NpmdctT15xGVgiFiSgtUqHl wHFfVq1lKyIFS4Orrwtao9wyoYZza0j4sg4WA0tM0Pjivziz50wXe3zakgsijuP/Asnb 6NBA== X-Gm-Message-State: AOJu0YyhzfKPSA2kOw4wEHRpuk9CYiWnOsZ3ETMpqeHu9F7bIITENQZ0 hkCMLVEMZdiShlkjK7VYefdRasvdjelAwkCMZThhc0tczvXuPLNEWeDX6cc2ja3E6Ipp25uhOWZ J X-Received: by 2002:a5d:644b:0:b0:33b:87c1:c4d with SMTP id d11-20020a5d644b000000b0033b87c10c4dmr1702299wrw.0.1708018541906; Thu, 15 Feb 2024 09:35:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id q16-20020adfea10000000b0033cfa00e497sm2384129wrm.64.2024.02.15.09.35.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:35:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/35] target/arm: Split out make_svemte_desc Date: Thu, 15 Feb 2024 17:35:08 +0000 Message-Id: <20240215173538.2430599-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215173538.2430599-1-peter.maydell@linaro.org> References: <20240215173538.2430599-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Share code that creates mtedesc and embeds within simd_desc. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Gustavo Romero Message-id: 20240207025210.8837-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.h | 2 ++ target/arm/tcg/translate-sme.c | 15 +++-------- target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++---------------- 3 files changed, 31 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 96ba39b37e9..7b811b8ac51 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -28,6 +28,8 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, + uint32_t msz, bool is_write, uint32_t data); /* This function corresponds to CheckStreamingSVEEnabled. */ static inline bool sme_sm_enabled_check(DisasContext *s) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 8f0dfc884ec..46c7fce8b4e 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -206,7 +206,7 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) TCGv_ptr t_za, t_pg; TCGv_i64 addr; - int svl, desc = 0; + uint32_t desc; bool be = s->be_data == MO_BE; bool mte = s->mte_active[0]; @@ -224,18 +224,11 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); - if (mte) { - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); - desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); - desc <<= SVE_MTEDESC_SHIFT; - } else { + if (!mte) { addr = clean_data_tbi(s, addr); } - svl = streaming_vec_reg_size(s); - desc = simd_desc(svl, svl, desc); + + desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0); fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr, tcg_constant_i32(desc)); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index a88e523cbab..508f7b6bbdc 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4437,18 +4437,18 @@ static const uint8_t dtype_esz[16] = { 3, 2, 1, 3 }; -static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, - int dtype, uint32_t mte_n, bool is_write, - gen_helper_gvec_mem *fn) +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, + uint32_t msz, bool is_write, uint32_t data) { - unsigned vsz = vec_full_reg_size(s); - TCGv_ptr t_pg; uint32_t sizem1; - int desc = 0; + uint32_t desc = 0; - assert(mte_n >= 1 && mte_n <= 4); - sizem1 = (mte_n << dtype_msz(dtype)) - 1; + /* Assert all of the data fits, with or without MTE enabled. */ + assert(nregs >= 1 && nregs <= 4); + sizem1 = (nregs << msz) - 1; assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); + assert(data < 1u << SVE_MTEDESC_SHIFT); + if (s->mte_active[0]) { desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); @@ -4456,7 +4456,18 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); desc <<= SVE_MTEDESC_SHIFT; - } else { + } + return simd_desc(vsz, vsz, desc | data); +} + +static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, + int dtype, uint32_t nregs, bool is_write, + gen_helper_gvec_mem *fn) +{ + TCGv_ptr t_pg; + uint32_t desc; + + if (!s->mte_active[0]) { addr = clean_data_tbi(s, addr); } @@ -4465,7 +4476,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. */ - desc = simd_desc(vsz, vsz, zt | desc); + desc = make_svemte_desc(s, vec_full_reg_size(s), nregs, + dtype_msz(dtype), is_write, zt); t_pg = tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); @@ -5224,25 +5236,16 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, int scale, TCGv_i64 scalar, int msz, bool is_write, gen_helper_gvec_mem_scatter *fn) { - unsigned vsz = vec_full_reg_size(s); TCGv_ptr t_zm = tcg_temp_new_ptr(); TCGv_ptr t_pg = tcg_temp_new_ptr(); TCGv_ptr t_zt = tcg_temp_new_ptr(); - int desc = 0; - - if (s->mte_active[0]) { - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); - desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); - desc <<= SVE_MTEDESC_SHIFT; - } - desc = simd_desc(vsz, vsz, desc | scale); + uint32_t desc; tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt)); + + desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale); fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); }