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Fri, 15 Mar 2024 06:10:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Cc: qemu-riscv@nongnu.org, Anton Johansson , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Claudio Fontana , Richard Henderson , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Manos Pitsidianakis , Zhao Liu , qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.1 12/21] system: Introduce QemuArchBit enum Date: Fri, 15 Mar 2024 14:09:00 +0100 Message-ID: <20240315130910.15750-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240315130910.15750-1-philmd@linaro.org> References: <20240315130910.15750-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Current QEMU_ARCH_foo definitions are used as masks. Extract the bit values, so we can easily iterate over. Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/arch_init.h | 69 ++++++++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 22 deletions(-) diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 8850cb1a14..cf597c40a3 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -1,30 +1,55 @@ #ifndef QEMU_ARCH_INIT_H #define QEMU_ARCH_INIT_H +typedef enum QemuArchBit { + QEMU_ARCH_BIT_ALPHA = 0, + QEMU_ARCH_BIT_ARM = 1, + QEMU_ARCH_BIT_CRIS = 2, + QEMU_ARCH_BIT_I386 = 3, + QEMU_ARCH_BIT_M68K = 4, + QEMU_ARCH_BIT_MICROBLAZE = 6, + QEMU_ARCH_BIT_MIPS = 7, + QEMU_ARCH_BIT_PPC = 8, + QEMU_ARCH_BIT_S390X = 9, + QEMU_ARCH_BIT_SH4 = 10, + QEMU_ARCH_BIT_SPARC = 11, + QEMU_ARCH_BIT_XTENSA = 12, + QEMU_ARCH_BIT_OPENRISC = 13, + QEMU_ARCH_BIT_TRICORE = 16, + QEMU_ARCH_BIT_NIOS2 = 17, + QEMU_ARCH_BIT_HPPA = 18, + QEMU_ARCH_BIT_RISCV = 19, + QEMU_ARCH_BIT_RX = 20, + QEMU_ARCH_BIT_AVR = 21, + QEMU_ARCH_BIT_HEXAGON = 22, + QEMU_ARCH_BIT_LOONGARCH = 23, -enum { + QEMU_ARCH_BIT_LAST = QEMU_ARCH_BIT_LOONGARCH +} QemuArchBit; + +enum QemuArchMask { QEMU_ARCH_ALL = -1, - QEMU_ARCH_ALPHA = (1 << 0), - QEMU_ARCH_ARM = (1 << 1), - QEMU_ARCH_CRIS = (1 << 2), - QEMU_ARCH_I386 = (1 << 3), - QEMU_ARCH_M68K = (1 << 4), - QEMU_ARCH_MICROBLAZE = (1 << 6), - QEMU_ARCH_MIPS = (1 << 7), - QEMU_ARCH_PPC = (1 << 8), - QEMU_ARCH_S390X = (1 << 9), - QEMU_ARCH_SH4 = (1 << 10), - QEMU_ARCH_SPARC = (1 << 11), - QEMU_ARCH_XTENSA = (1 << 12), - QEMU_ARCH_OPENRISC = (1 << 13), - QEMU_ARCH_TRICORE = (1 << 16), - QEMU_ARCH_NIOS2 = (1 << 17), - QEMU_ARCH_HPPA = (1 << 18), - QEMU_ARCH_RISCV = (1 << 19), - QEMU_ARCH_RX = (1 << 20), - QEMU_ARCH_AVR = (1 << 21), - QEMU_ARCH_HEXAGON = (1 << 22), - QEMU_ARCH_LOONGARCH = (1 << 23), + QEMU_ARCH_ALPHA = (1 << QEMU_ARCH_BIT_ALPHA), + QEMU_ARCH_ARM = (1 << QEMU_ARCH_BIT_ARM), + QEMU_ARCH_CRIS = (1 << QEMU_ARCH_BIT_CRIS), + QEMU_ARCH_I386 = (1 << QEMU_ARCH_BIT_I386), + QEMU_ARCH_M68K = (1 << QEMU_ARCH_BIT_M68K), + QEMU_ARCH_MICROBLAZE = (1 << QEMU_ARCH_BIT_MICROBLAZE), + QEMU_ARCH_MIPS = (1 << QEMU_ARCH_BIT_MIPS), + QEMU_ARCH_PPC = (1 << QEMU_ARCH_BIT_PPC), + QEMU_ARCH_S390X = (1 << QEMU_ARCH_BIT_S390X), + QEMU_ARCH_SH4 = (1 << QEMU_ARCH_BIT_SH4), + QEMU_ARCH_SPARC = (1 << QEMU_ARCH_BIT_SPARC), + QEMU_ARCH_XTENSA = (1 << QEMU_ARCH_BIT_XTENSA), + QEMU_ARCH_OPENRISC = (1 << QEMU_ARCH_BIT_OPENRISC), + QEMU_ARCH_TRICORE = (1 << QEMU_ARCH_BIT_TRICORE), + QEMU_ARCH_NIOS2 = (1 << QEMU_ARCH_BIT_NIOS2), + QEMU_ARCH_HPPA = (1 << QEMU_ARCH_BIT_HPPA), + QEMU_ARCH_RISCV = (1 << QEMU_ARCH_BIT_RISCV), + QEMU_ARCH_RX = (1 << QEMU_ARCH_BIT_RX), + QEMU_ARCH_AVR = (1 << QEMU_ARCH_BIT_AVR), + QEMU_ARCH_HEXAGON = (1 << QEMU_ARCH_BIT_HEXAGON), + QEMU_ARCH_LOONGARCH = (1 << QEMU_ARCH_BIT_LOONGARCH), }; extern const uint32_t arch_type;