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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf5f6155b6sm4943761a91.29.2024.05.26.12.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:36:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH RISU v2 11/13] sparc64: Add VIS3 instructions Date: Sun, 26 May 2024 12:36:35 -0700 Message-Id: <20240526193637.459064-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526193637.459064-1-richard.henderson@linaro.org> References: <20240526193637.459064-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- sparc64.risu | 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 5b90b70..ca7ed35 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -155,3 +155,91 @@ FNMSUBs FMAF 10 rd:5 110111 rs1:5 rs3:5 1001 rs2:5 FNMSUBd FMAF 10 rd:5 110111 rs1:5 rs3:5 1010 rs2:5 FNMADDs FMAF 10 rd:5 110111 rs1:5 rs3:5 1101 rs2:5 FNMADDd FMAF 10 rd:5 110111 rs1:5 rs3:5 1110 rs2:5 + +# +# VIS3 +# + +ADDXC VIS3 10 rd:5 110110 rs1:5 0 0001 00 cc 1 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } + +FCHKSM16 VIS3 10 rd:5 110110 rs1:5 0 0100 0100 rs2:5 +FMEAN16 VIS3 10 rd:5 110110 rs1:5 0 0100 0000 rs2:5 + +FHADDs VIS3 10 rd:5 110100 rs1:5 0 0110 0001 rs2:5 +FHADDd VIS3 10 rd:5 110100 rs1:5 0 0110 0010 rs2:5 +FHSUBs VIS3 10 rd:5 110100 rs1:5 0 0110 0101 rs2:5 +FHSUBd VIS3 10 rd:5 110100 rs1:5 0 0110 0110 rs2:5 +FNHADDs VIS3 10 rd:5 110100 rs1:5 0 0111 0001 rs2:5 +FNHADDd VIS3 10 rd:5 110100 rs1:5 0 0111 0010 rs2:5 + +FNADDs VIS3 10 rd:5 110100 rs1:5 0 0101 0001 rs2:5 +FNADDd VIS3 10 rd:5 110100 rs1:5 0 0101 0010 rs2:5 +FNMULs VIS3 10 rd:5 110100 rs1:5 0 0101 1001 rs2:5 +FNMULd VIS3 10 rd:5 110100 rs1:5 0 0101 1010 rs2:5 + +FPADD64 VIS3 10 rd:5 110110 rs1:5 0 0100 0010 rs2:5 +FPSUB64 VIS3 10 rd:5 110110 rs1:5 0 0100 0110 rs2:5 + +FPADDS16 VIS3 10 rd:5 110110 rs1:5 0 0101 1000 rs2:5 +FPADDS16s VIS3 10 rd:5 110110 rs1:5 0 0101 1001 rs2:5 +FPADDS32 VIS3 10 rd:5 110110 rs1:5 0 0101 1010 rs2:5 +FPADDS32s VIS3 10 rd:5 110110 rs1:5 0 0101 1011 rs2:5 +FPSUBS16 VIS3 10 rd:5 110110 rs1:5 0 0101 1100 rs2:5 +FPSUBS16s VIS3 10 rd:5 110110 rs1:5 0 0101 1101 rs2:5 +FPSUBS32 VIS3 10 rd:5 110110 rs1:5 0 0101 1110 rs2:5 +FPSUBS32s VIS3 10 rd:5 110110 rs1:5 0 0101 1111 rs2:5 + +FPCMPULE8 VIS3 10 rd:5 110110 rs1:5 1 0010 0000 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPUGT8 VIS3 10 rd:5 110110 rs1:5 1 0010 1000 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPEQ8 VIS3 10 rd:5 110110 rs1:5 1 0010 0010 rs2:5 \ + !constraints { reg_ok($rd) } +FPCMPNE8 VIS3 10 rd:5 110110 rs1:5 1 0010 1010 rs2:5 \ + !constraints { reg_ok($rd) } + +FSLL16 VIS3 10 rd:5 110110 rs1:5 0 0010 0001 rs2:5 +FSRL16 VIS3 10 rd:5 110110 rs1:5 0 0010 0011 rs2:5 +FSLAS16 VIS3 10 rd:5 110110 rs1:5 0 0010 1001 rs2:5 +FSRA16 VIS3 10 rd:5 110110 rs1:5 0 0010 1011 rs2:5 +FSLL32 VIS3 10 rd:5 110110 rs1:5 0 0010 0101 rs2:5 +FSRL32 VIS3 10 rd:5 110110 rs1:5 0 0010 0111 rs2:5 +FSLAS32 VIS3 10 rd:5 110110 rs1:5 0 0010 1101 rs2:5 +FSRA32 VIS3 10 rd:5 110110 rs1:5 0 0010 1111 rs2:5 + +LZCNT VIS3 10 rd:5 110110 00000 0 0001 0111 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs2); } + +PDISTN VIS3 10 rd:5 110110 rs1:5 0 0011 1111 rs2:5 \ + !constraints { reg_ok($rd) } + +UMULXHI VIS3 10 rd:5 110110 rs1:5 0 0001 0110 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +XMULX VIS3 10 rd:5 110110 rs1:5 1 0001 0101 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } +XMULXHI VIS3 10 rd:5 110110 rs1:5 1 0001 0110 rs2:5 \ + !constraints { reg_ok($rd) && reg_ok($rs1) && reg_ok($rs2); } + +MOVsTOuw VIS3 10 rd:5 110110 00000 1 0001 0001 rs2:5 \ + !constraints { reg_ok($rd) } +MOVsTOsw VIS3 10 rd:5 110110 00000 1 0001 0011 rs2:5 \ + !constraints { reg_ok($rd) } +MOVwTOs VIS3 10 rd:5 110110 00000 1 0001 1001 rs2:5 \ + !constraints { reg_ok($rs2) } +MOVdTOx VIS3 10 rd:5 110110 00000 1 0001 0000 rs2:5 \ + !constraints { reg_ok($rd) } +MOVxTOd VIS3 10 rd:5 110110 00000 1 0001 1000 rs2:5 \ + !constraints { reg_ok($rs2) } + +# Defer +# LDXEFSR_r VIS3 11 00011 100001 rs1:5 0 00000000 rs2:5 +# LDXEFSR_i VIS3 11 00011 100001 rs1:5 1 simm:13 + +# %gsr not handled by risu +# CMASK8 VIS3 10 00000 110110 00000 0 0001 1011 rs2:5 \ +# !constraints { reg_ok($rs2); } +# CMASK16 VIS3 10 00000 110110 00000 0 0001 1101 rs2:5 \ +# !constraints { reg_ok($rs2); } +# CMASK32 VIS3 10 00000 110110 00000 0 0001 1111 rs2:5 \ +# !constraints { reg_ok($rs2); }