From patchwork Sat Jun 22 12:06:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 806712 Delivered-To: patch@linaro.org Received: by 2002:a5d:508d:0:b0:362:4979:7f74 with SMTP id a13csp1151465wrt; Sat, 22 Jun 2024 05:08:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWN14dsqrHWIVgjcqvWCWKlMj4T0g7fyUin7FPmz/QhtgP9qfJ3VWFJuCo200eBjEKzPlbUFAsipA/BQ46oTkdY X-Google-Smtp-Source: AGHT+IH7lsk8nRGfBIwoNrVbXbdDM/nL21PHnlv113C8W4sQXKOkws/iVdPEuK9dyFxTjeGZ3cu3 X-Received: by 2002:a05:6808:1447:b0:3d2:2a0b:cf1b with SMTP id 5614622812f47-3d543b7bed3mr377647b6e.37.1719058104014; Sat, 22 Jun 2024 05:08:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1719058103; cv=none; d=google.com; s=arc-20160816; b=u9en2Th8Sq2UKXRrqzHxBVzoN3pghrL7bblDtWkpC3npRZzqPW9EX3ftNfV24l5Uwh spYjTX2ElTkPC+Npe5P04HrXBKu6LlDd44fcX2U4+WlYaGGN50B3hnNSidP/VA94wRlO x291KQZmXDoas/Z9ioqntpt8ifU1D6l/lBp6r72U4MBpG+caIfqJ/EI+s/sfQeHCw7fF HEuSdlLrWip/LD9iv7+ltKlOdOo32nmXZOKu+PPF/P+5Y7gCgQp2aYfcHxwppDhY+V4j Mx5Zy9VSBpIziLjiRRUDXu7i/tjKoqpcOeA9ihuLpcam0TtpJJ9iVymAjgI7yFs7GiVO LkrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y/peQK2HWWhn2ma2SjoOX9PrYOZzJnJW241P1DXKLDo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LWYSFoQFjL/AkD0+Zbb3rSzHbqh0aWhYvWsKs32HFg6NzW4ebW7jT8OBatSPOmCwIO SvkHO2LX7v/lLwM2tdLaTrMuI4C+6jvTw9Fr3/CrXRT9XR8qfNp94DCUUm8Hx93gir8J Lv5ANggjOD+ZHwx/nd77+iXdn572zt1Ditx+tTbAFVPows1LblyogMaMQ6rwnJccUulS eh4n6JjrTO3Q69RNsGniJgn92RzBbZFx09KWO5+OjWAb3f0Qd+mfPb6YskaRJqmsnMVr oZWaVjI9N1nTBC19hOzocyDAD1bXy+TX2o3JYiEUP0KXXDc4zxGw76cY24RfR4VeLn2U hTMw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="M/ap3v1F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-444c2b73a50si43002211cf.192.2024.06.22.05.08.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 22 Jun 2024 05:08:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="M/ap3v1F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sKzWM-000814-9J; Sat, 22 Jun 2024 08:07:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sKzWG-0007vu-W2 for qemu-devel@nongnu.org; Sat, 22 Jun 2024 08:07:01 -0400 Received: from mail-lj1-x236.google.com ([2a00:1450:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sKzWB-0000LZ-EP for qemu-devel@nongnu.org; Sat, 22 Jun 2024 08:06:57 -0400 Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2ec3c0dada3so36589761fa.0 for ; Sat, 22 Jun 2024 05:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719058014; x=1719662814; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=y/peQK2HWWhn2ma2SjoOX9PrYOZzJnJW241P1DXKLDo=; b=M/ap3v1FDFzv52L9BGdMKUQNQMK/seFFXNZ0/qnK1Ce2cZjPAUeog8/XBeTXEktBqs CWvqt807w5jAB1vgWVSsmwKeVy17uQwnkZ/3RkqwDKWjqFfffJFZ1Syw47ddrMONpIFc AXTeT3PrCFMK/Ov/tTpC3OZmUJd+24H/kP/FDWOeO4Q+R7CwZCCCrtl2sUzFmy1EBqLa OR0r8glw5fD/x7UTrjHoxc9bmdlM+MfbbvinC1ZqjZQFO21HQbdhza1FswjETyTVqX8S CByEhtMZ4LXZgmCRHQgKZPNYnVplsdrphZuhp/ZGOUo1Q8BxVzPCV4O3aFwIP/m86lN4 cqlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719058014; x=1719662814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y/peQK2HWWhn2ma2SjoOX9PrYOZzJnJW241P1DXKLDo=; b=v2ulQSSCQhMXKEkmXrylWE+/EzhEYvV02Kdaz9tZNTcRoKgLzuNuPiDE/KVLIKdWDv k4jERUBxiJWtibb4gQV1+9D/XJ5XQt4zVvU1dvNwYz1cNCfZdcHSWRwlAN5iu6OudzTi 49GNGXmdQukFXdRuPpmDhbAImkhuBfLJqYk8c88zijPTpmtBvOoJVRJX7qabP1if26ja n0QtAlUnCybeiGqRudm2OeAvcDuDmZG+6SCAumdPIpzYjsjeLpUGPGcbhSBDnsBAw8sN k/NrdKDxvBVYTTi8ZpucZDsVZEY3lMCfgSHJDvkt+tWg3869NzSRR6XmRbfIJlM7axf9 j3zw== X-Gm-Message-State: AOJu0YydNV8Y20bY/R6lOtwQlndVrZcwPPMMzDSl7EegL0R67ceu8LTo 8FvNgWYIaoxZbkoySNY0JXtIyYiu6J2kVK9yhU7kvRrGtCmO4LFm8ow/F0goxcIkV6LoFMX85Mg pa2A= X-Received: by 2002:ac2:4e8d:0:b0:52c:df4e:3343 with SMTP id 2adb3069b0e04-52cdf4e346emr803123e87.16.1719058013586; Sat, 22 Jun 2024 05:06:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3663a2f698dsm4393006f8f.70.2024.06.22.05.06.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jun 2024 05:06:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/18] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine Date: Sat, 22 Jun 2024 13:06:43 +0100 Message-Id: <20240622120643.3797539-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240622120643.3797539-1-peter.maydell@linaro.org> References: <20240622120643.3797539-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Xiong Yining Enable CPU cluster support on SbsaQemu platform, so that users can specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this topology can be passed to the firmware through /cpus/topology Device Tree. Signed-off-by: Xiong Yining Reviewed-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm Message-id: 20240607103825.1295328-2-xiongyining1480@phytium.com.cn Tested-by: Marcin Juszkiewicz Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 4 ++++ hw/arm/sbsa-ref.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index 2bf22a1d0b0..2bf3fc8d59d 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -62,6 +62,7 @@ The devicetree reports: - platform version - GIC addresses - NUMA node id for CPUs and memory + - CPU topology information Platform version '''''''''''''''' @@ -88,3 +89,6 @@ Platform version changes: 0.3 The USB controller is an XHCI device, not EHCI. + +0.4 + CPU topology information is present in devicetree. diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 87884400e30..ae37a923015 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -219,7 +219,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 4); if (ms->numa_state->have_numa_distance) { int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -276,6 +276,14 @@ static void create_fdt(SBSAMachineState *sms) g_free(nodename); } + /* Add CPU topology description through fdt node topology. */ + qemu_fdt_add_subnode(sms->fdt, "/cpus/topology"); + + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "sockets", ms->smp.sockets); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "clusters", ms->smp.clusters); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "cores", ms->smp.cores); + qemu_fdt_setprop_cell(sms->fdt, "/cpus/topology", "threads", ms->smp.threads); + sbsa_fdt_add_gic_node(sms); } @@ -898,6 +906,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_ram_id = "sbsa-ref.ram"; mc->default_cpus = 4; + mc->smp_props.clusters_supported = true; mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;