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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4319360cc2esm146835865e9.44.2024.10.29.08.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 08:10:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 14/18] docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabre Date: Tue, 29 Oct 2024 15:10:44 +0000 Message-Id: <20241029151048.1047247-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029151048.1047247-1-peter.maydell@linaro.org> References: <20241029151048.1047247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add placeholder docs for the mcimx6ul-evk and mcimx7d-sabre boards. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Reviewed-by: Alistair Francis Message-id: 20241018141332.942844-7-peter.maydell@linaro.org --- MAINTAINERS | 2 ++ docs/system/arm/mcimx6ul-evk.rst | 5 +++++ docs/system/arm/mcimx7d-sabre.rst | 5 +++++ docs/system/target-arm.rst | 2 ++ 4 files changed, 14 insertions(+) create mode 100644 docs/system/arm/mcimx6ul-evk.rst create mode 100644 docs/system/arm/mcimx7d-sabre.rst diff --git a/MAINTAINERS b/MAINTAINERS index 66c7572c27b..1e88b5738cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -791,6 +791,7 @@ F: hw/arm/fsl-imx6ul.c F: hw/misc/imx6ul_ccm.c F: include/hw/arm/fsl-imx6ul.h F: include/hw/misc/imx6ul_ccm.h +F: docs/system/arm/mcimx6ul-evk.rst MCIMX7D SABRE / i.MX7 M: Peter Maydell @@ -804,6 +805,7 @@ F: include/hw/arm/fsl-imx7.h F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h +F: docs/system/arm/mcimx7d-sabre.rst MPS2 / MPS3 M: Peter Maydell diff --git a/docs/system/arm/mcimx6ul-evk.rst b/docs/system/arm/mcimx6ul-evk.rst new file mode 100644 index 00000000000..8871138ab3e --- /dev/null +++ b/docs/system/arm/mcimx6ul-evk.rst @@ -0,0 +1,5 @@ +NXP MCIMX6UL-EVK (``mcimx6ul-evk``) +=================================== + +The ``mcimx6ul-evk`` machine models the NXP i.MX6UltraLite Evaluation Kit +MCIMX6UL-EVK development board. It has a single Cortex-A7 CPU. diff --git a/docs/system/arm/mcimx7d-sabre.rst b/docs/system/arm/mcimx7d-sabre.rst new file mode 100644 index 00000000000..c5d35af1d44 --- /dev/null +++ b/docs/system/arm/mcimx7d-sabre.rst @@ -0,0 +1,5 @@ +NXP MCIMX7D Sabre (``mcimx7d-sabre``) +===================================== + +The ``mcimx7d-sabre`` machine models the NXP SABRE Board MCIMX7SABRE, +based an an i.MX7Dual SoC. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index ace36d1b17d..1f806cf4a46 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -97,6 +97,8 @@ undocumented; you can get a complete list by running arm/nrf arm/nuvoton arm/imx25-pdk + arm/mcimx6ul-evk + arm/mcimx7d-sabre arm/orangepi arm/raspi arm/collie