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[209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-462ad0d044csi9379121cf.164.2024.10.30.21.23.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 Oct 2024 21:23:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b2dFHgtB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t6Mi9-0008OC-E3; Thu, 31 Oct 2024 00:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t6Mi7-0008KJ-LX for qemu-devel@nongnu.org; Thu, 31 Oct 2024 00:23:03 -0400 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t6Mi5-0006sa-TI for qemu-devel@nongnu.org; Thu, 31 Oct 2024 00:23:03 -0400 Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2fb50e84ec7so3131851fa.1 for ; Wed, 30 Oct 2024 21:23:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730348579; x=1730953379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=szXkpmPSUeROwD+6VYjwTLHIGyNjyw7b2MJe2LmUrMg=; b=b2dFHgtB6RJju2nkBz4nPYMPLsrXddN4WQZlvN59N+Cy/OF26Kr597EIVHut1nI0pl UJ+/R0HNQ77Jr3qPjrhU5895tUIcEXV3r/CmXM8M5+2X7abhgWLWh86eviVGK2K2WlKs W2q+RVxilbAVOr0chSiP2kQxSWO7KxELd3SgXlpHKHAcgyyE/j5eWn1FaMn/RcFdTFxY 6/HdaLets86hI+CBQGzN19ZBcg7yJtCNDatoLyngu7XhqaG3FZowxkQqchfi1j6ZeODI /LC9XchAqC/KhV3e4DuUNrIqT1fEWyWz5XOX+g0sSzNJ+aIHKrvCIacJdK1OcSlJKJBd muOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730348579; x=1730953379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=szXkpmPSUeROwD+6VYjwTLHIGyNjyw7b2MJe2LmUrMg=; b=Z7o0Rnux0oswQd16iy9fj8GC5DAO0bis5b7ZlnTty8c7vzBs3zt0fOq21Yp5Li5G0p kZNS/KlGiZNAOBcU19A1WZTYdWtlSuxddkBLwznBTUyRm/sA1eHoyz8YtAz8vNWdcmrY gy+XpQNDDlbzcxJHZcymfuGvRiZTtUjeB6z/JeJcnS7Pn/h1wFKEV4LUkezMhiggMzKB kOU0NrFM+Vhlk8eyW8Y1D39dHQL0EEhpMst41jeCEvHhWk0kzDzOUlTlkTbR2qqbqlN4 JajUvh3Nc1NnJubUFZY8ADLIOb8lgcTE94pFKHSriaB2mg/kQ7yNTJpMCWejrow9Bdth yNHg== X-Gm-Message-State: AOJu0YzegyI/twVDlq/SBdgCjNBWCC51YFcuiaVdzcfGFhUQq/Ecegvg 2ta6Fv1nF45lmazrtQRT/TYLTxun7KiChpOmGgg3IeDVeA6hOu1O9KzmKFMSgoJXEZc/AjLVq3e u X-Received: by 2002:a2e:a543:0:b0:2fa:cc50:41b with SMTP id 38308e7fff4ca-2fcbdf5fa9amr85198681fa.5.1730348579299; Wed, 30 Oct 2024 21:22:59 -0700 (PDT) Received: from localhost.localdomain ([91.223.100.208]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fdef8c393asm937971fa.107.2024.10.30.21.22.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 30 Oct 2024 21:22:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 05/14] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Date: Thu, 31 Oct 2024 01:21:21 -0300 Message-ID: <20241031042130.98450-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241031042130.98450-1-philmd@linaro.org> References: <20241031042130.98450-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé There is no issue having multiple enum declarations with the same value. As we are going to remove the OPC_MULT_G_2E definition in few commits, restore the OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP definitions and use them where they belong. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Message-Id: <20241026175349.84523-4-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6d7e913263e..509488fdc7a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -389,16 +389,14 @@ enum { OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, - /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ - /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, /* MIPS DSP GPR-Based Shift Sub-class */ OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, /* MIPS DSP Multiply Sub-class insns */ - /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ - /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, /* DSP Bit/Manipulation Sub-class */ @@ -556,7 +554,6 @@ enum { OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, }; -#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Arithmetic Sub-class */ @@ -11587,8 +11584,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); switch (op1) { - /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ - case OPC_MULT_G_2E: + case OPC_ADDUH_QB_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_ADDUH_QB: @@ -12271,11 +12267,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, gen_load_gpr(v2_t, v2); switch (op1) { - /* - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have - * the same mask and op1. - */ - case OPC_MULT_G_2E: + case OPC_MUL_PH_DSP: check_dsp_r2(ctx); switch (op2) { case OPC_MUL_PH: @@ -13811,7 +13803,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ - if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { + if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { op2 = MASK_ADDUH_QB(ctx->opcode); switch (op2) { case OPC_ADDUH_QB: